Browse Prior Art Database

Non-Inverting BIFET Buffer Circuit

IP.com Disclosure Number: IPCOM000101254D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Puri, YK: AUTHOR [+2]

Abstract

BIFET technology is able to put both complementary MOS transistors and bipolar transistors on the same integrated circuit chip. One of the more promising ways to use the BIFET process for logic circuit applications is to use mostly CMOS circuits for the logic (because they are small) with an occasional bipolar stage for fast drive capability in paths where timing is critical. This approach requires a good fast non-inverting buffer in order to be effective. The purpose of this disclosure is to describe a BIFET non-inverting buffer circuit which is simple and fast.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Non-Inverting BIFET Buffer Circuit

       BIFET technology is able to put both complementary MOS
transistors and bipolar transistors on the same integrated circuit
chip.  One of the more promising ways to use the BIFET process for
logic circuit applications is to use mostly CMOS circuits for the
logic (because they are small) with an occasional bipolar stage for
fast drive capability in paths where timing is critical.  This
approach requires a good fast non-inverting buffer in order to be
effective. The purpose of this disclosure is to describe a BIFET
non-inverting buffer circuit which is simple and fast.

      A BIFET circuit which is intended to supplement CMOS logic
circuits must be compatible with the CMOS logic circuits.  The input
and output signal levels must be the same as CMOS voltage levels, it
should have zero DC power dissipation, and it must use the same power
supply voltage. Bipolar transistors must be kept out of saturation in
order to realize the minimum possible delay.  The circuit shown in
Fig. 1 accomplishes these goals.

      Transistors Q1 and Q2 are CMOS devices while transistors Q3 and
Q4 are n-p-n bipolar devices.  The circuit is intended to be driven
by a standard CMOS logic gate, and the load on the buffer is intended
to be composed of only CMOS logic gates, along with the inevitable
wiring capacitance.

      When the input is an up-level (VDD), transistor Q1 is cut off
and transistor Q2 is turned on.  This pulls the base of transistor Q4
to ground, cutting it off.  Meanwhile, transistor Q3 acts as an
emitter follower, rapidly charging the output load capacitance toward
VDD.  Bipolar transistor Q3 will not saturate because it is
impossible for the preceding stage to drive the input high enough to
forward-bias the base-collector...