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Active Restore Circuit for Open Collector Signals

IP.com Disclosure Number: IPCOM000101266D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 85K

Publishing Venue

IBM

Related People

Riley, MW: AUTHOR

Abstract

A method is disclosed that describes a circuit that quickly restores an open collector circuit for the logic "0" state to the logic "1" state.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Active Restore Circuit for Open Collector Signals

       A method is disclosed that describes a circuit that
quickly restores an open collector circuit for the logic "0" state to
the logic "1" state.

      Fig. 1 shows the active restore circuit.  The circuit shown is
assumed to be used on an I/O channel similar to the IBM MICRO
CHANNEL*.  The signals "-ADL" and "-CMD" are MICRO CHANNEL control
signals.  The "-BUS SIGNAL" is used to represent an open collector
MICRO CHANNEL sig- nal with the maximum bus capacitance load (240
pF).

      The restore circuit is designed to restore the open collector
-BUS SIGNAL from the logic zero state to the logic one state during
the time -ADL is at the logic zero state and the -CMD signal is at
the logic one state.  When this condition is met, the restore circuit
is in the "ON" state. In the "ON" state, the transistor 14 conducts
and charges the bus capacitance through the 10-ohm resistor 13.  In
the "OFF" state (all other combinations of -ADL and -CMD), the
transistor does not conduct and -BUS SIGNAL appears to be pulled up
through a 2K-ohm resis tor.  This is of significant importance to
devices that drive the -BUS SIGNAL to the logic zero value.  For
example, to drive -BUS SIGNAL to the logic zero state with the 2K ohm
resistor requires 2.5 milliamps of current.  To drive the signal to
the logic zero state with a 10-ohm resistor requires 500 milliamps.
500 milliamps is greater than the current drive of logic devices.

      When -ADL is at the logic zero state, -CMD is at the active one
state, and the latch 11 output is at the logic one state, the
transistor 14 is turned on (the latch was put in the logic one state
by the previous cycle).  When this condition occurs, the voltage on
the -BUS SIGNAL is characterized by the following equation:

      Vbus signal = 5...