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High-Speed CMOS Driver With Current-Diverting Circuit

IP.com Disclosure Number: IPCOM000101272D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 7 page(s) / 227K

Publishing Venue

IBM

Related People

Herrman, BD: AUTHOR [+2]

Abstract

A major concern with the introduction of new circuit/chip designs into a package are the effects of simultaneous switching (S.S.). The inductance of the conductor circuit paths within the package are essentially passive and not easily controlled. The number of signal input/output pins (I/Os) of a package are usually maximized at the expense of power I/Os. This results in higher effective inductance through which the switching current must flow. In order to avoid logic failures associated with an excessive number of off chip drivers (OCDs) switching, a restriction is typically placed on the number of OCDs that can switch simultaneously in a package. The restricted number is directly related to the effective package inductance (L) and to the OCD switching current (di/dt).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

High-Speed CMOS Driver With Current-Diverting Circuit

       A major concern with the introduction of new circuit/chip
designs into a package are the effects of simultaneous switching
(S.S.).  The inductance of the conductor circuit paths within the
package are essentially passive and not easily controlled.  The
number of signal input/output pins (I/Os) of a package are usually
maximized at the expense of power I/Os.  This results in higher
effective inductance through which the switching current must flow.
In order to avoid logic failures associated with an excessive number
of off chip drivers (OCDs) switching, a restriction is typically
placed on the number of OCDs that can switch simultaneously in a
package.  The restricted number is directly related to the effective
package inductance (L) and to the OCD switching current (di/dt).

      The advantages of this disclosure are:
1)   This OCD design reduces the detrimental effects of di/dt for
S.S.  drivers by close to 30 percent (design dependent) at the low
end of the Mil temperature spec while maintaining speed performance
objectives of the high end.
2)   Use of this invention permits the utilization of cheaper
packages (higher inductance) for high speed circuits.
3)   No additional processing or alteration to processing required
for this enhancement.
4)   This circuit enhancement requires only one additional small size
device and has minimal impact to circuit area or size.

      In general, CMOS OCDs di/dt will increase in magnitude as the
temperature gets colder (lower) and vice versa. Mil-specs require
operation as low as -55oC and as high as 125oC.  Although the
packaged chip's speed performance is specified at the hottest
temperature, errors due to S.S. predominantly occur at the lowest
temperature.

      The purpose of this invention is to provide a means whereby
maximum performance is maintained at the highest spec temperature for
a given design, but are protected from the increased di/dt effects at
the lowest temperature.  In addition, the impact to speed performance
characteristics are minimized.

      Fig. 1 is an abbreviated schematic of an OCD with an N
pull-down (T1) and N pull-up (T2).  The OCD circuit is typically
designed such that T2 has a lower gate-to-source voltage than T1
(lower gate drive).  T1 has a higher di/dt capability.  Thus, most
S.S. problems tend to occur when T1 turns on.

      The circuit operates in the following manner.  Assume the
output is initially at a high level.  The highest level obtainable is
VDD minus threshold because T2 is an NFET. When the voltage level on
T2's gate is VDD, the output of the OCD is VDD minus a threshold and
T2 is cut off.  Also, T1 and T3 are initially off and T4 is initially
on.  When the input (IN) goes from high to low, the inverters T3 and
T4 will see an input voltage equivalent to ground.  T4 turns off and
T3 turns on.  Most of current sourced by T3 goes to charging th...