Browse Prior Art Database

Methods to Reduce Junction Leakage in Sidewall Contact Structures

IP.com Disclosure Number: IPCOM000101275D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 133K

Publishing Venue

IBM

Related People

Monkowski, MD: AUTHOR

Abstract

A process and structure are suggested which form an oxide spacer independent of the extrinsic base drive-in and the top surface oxidation in semiconductor devices. This makes it possible to predetermine the width and depth of the oxide bird's beak before the P+ (extrinsic base) drive-in without being concerned that the P+ will diffuse in too far.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Methods to Reduce Junction Leakage in Sidewall Contact Structures

       A process and structure are suggested which form an oxide
spacer independent of the extrinsic base drive-in and the top surface
oxidation in semiconductor devices.  This makes it possible to
predetermine the width and depth of the oxide bird's beak before the
P+ (extrinsic base) drive-in without being concerned that the P+ will
diffuse in too far.

      In the fabrication of sidewall contact structures (SICOS)(1,2),
encroachment of dopant from a sidewall contact to the topside contact
creates an N+ P+ abrupt junction 1 (Fig. 1) which may cause increased
junction leakage at this point under reverse bias.  The (SICOS)
consists of a base polysilicon 2 between oxide layers 3,4 and emitter
polysilicon 5.  The N+ emitter 6, P intrinsic base 7, P+ extrinsic
base 8 and the N collector 9 are located in the respective positions
shown.

      Several methods are proposed to improve the performance of the
devices by forming a more graded junction.  In a method relating to
extrinsic base diffusion, base polysilicon 2 (Fig. 2) is deposited
over the Si pedestal 10 , which is capped with an oxide-1 layer 11
and nitride-1 layer 12.  The polysi also covers the field oxide 4.

      The process calls for an in-situ P+ poly which results in the
abrupt junction illustrated in Fig. 1.  If a lightly doped in-situ
poly is used to form the extrinsic base 8 (Fig. 2), and this is
annealed at a temperature high enough to diffuse the dopant into the
pedestal, then the junction will not be so abrupt.  The sheet
resistance of the base poly may then be reduced by a second, high
dose implant followed by an anneal at a temperature which will be
high enough to redistribute the dopant in the poly but not so high
that diffusion into the extrinsic base is minimized.

      In a second method a silicide used in place of the base poly
would need only be doped enough to form the extrinsic base since its
sheet resistance is low enough without doping.  A thin barrier layer
may also be deposited prior to base poly deposition to impede
diffusion provided that it is a good electrical conductor which would
not appreciably affect base resistance.

      There are methods to offset the stack relative to the silicon
pedestal.  There is a point in the process where the Si pedestal 10
(Fig. 3) has its oxide-1 layer 11 and nitride-1 layer 12 topped by an
oxide-2 layer 13 and a nitride-2 layer 14.  Sidewall oxide-3 15,
oxide5 4, and sidewall nitride-3 16 complete the structure to this
point. Nitride-2 and nitride-3 are then removed in a plasma etch
followed by a wet etching of oxide-2 and oxide-3.  The proposal
suggests overetching the nitride so that nitride-1 12 (Fig. 4) is
undercut significantly.  If oxide-1 11 is thicker...