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Testing Strategy for Cmos Open Fault

IP.com Disclosure Number: IPCOM000101280D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 8 page(s) / 274K

Publishing Venue

IBM

Related People

Truong, K: AUTHOR

Abstract

The problem of generating tests for defect failures on FET transistor networks has been unsolved for all but simple cases. The lack of a well-defined failure-preserving transformation from switches to logics makes stuck fault models ineffective in the testing of CMOS open faults, delay faults, and transition faults. Although there is progress in defining the problem, the testing of these different fault types is not often seen in practice. The observation, however, is very conclusive that CMOS open fault (s-o-f) and transition fault can be translated into stuck at fault (s-a-1 or s-a-0) models with the accommodation of two pattern tests (2PT): the first pattern initializes the circuit while the second pattern changes the value of the output node.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 29% of the total text.

Testing Strategy for Cmos Open Fault

       The problem of generating tests for defect failures on
FET transistor networks has been unsolved for all but simple cases.
The lack of a well-defined failure-preserving transformation from
switches to logics makes stuck fault models ineffective in the
testing of CMOS open faults, delay faults, and transition faults.
Although there is progress in defining the problem, the testing of
these different fault types is not often seen in practice.  The
observation, however, is very conclusive that CMOS open fault (s-o-f)
and transition fault can be translated into stuck at fault (s-a-1 or
s-a-0) models with the accommodation of two pattern tests (2PT):  the
first pattern initializes the circuit while the second pattern
changes the value of the output node.

      The 2PT generation is not economical and stray delays in the
circuit may create a hazard which can invalidate the 2PT.  The
Enhanced Test Generator (1) (ETG) takes advantage of some features of
the Level- Sensitive Scan Design (LSSD) to attack these problems with
some successes.  However, ETG can only solve part of the problem due
to two fundamental constraints of the LSSD technique:
      1.   LSSD scan design does not lend itself to 2PT application
because it cannot hold the values of the initialized pattern while
loading the second test pattern.  ETG considers the toggling primary
inputs (PIs), the additional AB-clocks, or CB-clocks in tester loop
to simulate 2PT, but these considerations offer very little advantage
due to circuit complexity and low I/O-to-circuit ratio in VLSI
application.  ETG indicates this difficulty with the result of 40-70%
CMOS open fault coverage.
      2.   Another problem is how to feed SRL(L1) and SRL(L2)
different values through LSSD scan path.  LSSD scan load is done with
A-B clock pairs, thus causing the SRL(L2) to be fed from SRL(L1) on
B-clock.  This prevents the possibility to change the SRL(L2) value
in a single B-clock.

      These problems can be overcome by using stable SRL (SSRL), but
this scheme introduces a large area overhead. Other modified SRL
designs for CMOS open fault testing also present further restriction
on circuit implementation and fail to address the transition fault
testing.

      The intention of this disclosure is to discuss a simple way to
support CMOS open and transition fault test generation using the same
SRL in a similar manner of the SSRL scheme, thus eliminating the area
overhead problem while providing the benefits of a straightforward
2PT test generation.  The scheme does not conform to the existing
LSSD rules due to its exclusive use of the SRL(L1) for scan path
while the modified scan clocks ensure the "polarity hold" property of
the SRL.  However, this violation does not compromise the LSSD design
principle.  In fact, these violations effect only conventional test
generator soft ware designed to treat an SRL as containing only one
bi...