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Using the Dma And Software Timer Tic to Refresh Dram On Systems Utilizing the Intel 80186 Nmos Processor

IP.com Disclosure Number: IPCOM000101281D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 44K

Publishing Venue

IBM

Related People

Tyson, JS: AUTHOR [+2]

Abstract

Disclosed is a method which uses one of the built-in Intel 80186 DMA channels in conjunction with the software timer tic to provide DRAM refresh. The DMA is programmed to provide continuous access of memory, and the software timer tic insures that the address range for the DMA access remains within the DRAM area. This arrangement provides an efficient and low-cost solution to refresh the DRAM in systems utilizing the Intel 80186 processor.

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Using the Dma And Software Timer Tic to Refresh Dram On Systems Utilizing the Intel 80186 Nmos Processor

       Disclosed is a method which uses one of the built-in
Intel 80186 DMA channels in conjunction with the software timer tic
to provide DRAM refresh. The DMA is programmed to provide continuous
access of memory, and the software timer tic insures that the address
range for the DMA access remains within the DRAM area.  This
arrangement provides an efficient and low-cost solution to refresh
the DRAM in systems utilizing the Intel 80186 processor.

      One of the built-in Intel 80186 DMA channels is used in
conjunction with the software timer tic to provide DRAM refresh. The
DMA is programmed to provide continuous word (16 bits) transfers from
DRAM to a fixed location (in ROS). A transfer from DRAM constitutes a
refresh cycle.  The fixed location was selected to be ROS since it is
a valid zero wait state cycle and the transfer does not alter any
storage or I/O location.

      The software timer tic program was modified such that when a
timer tic interrupt occurs, the four most significant bits in the DMA
source address register are cleared.  Since these bits are in a
separate 80186 register, clearing these bits does not affect the
address bits significant to the DRAM refresh.  Also, clearing these
bits will insure that the address range accessed by the DMA channel
will remain within 128K bytes.  Timer tics occurs approximately ever
55 milliseconds.

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