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Reduction of Cache Coherence Traffic in MP Systems Via Large Block Authority

IP.com Disclosure Number: IPCOM000101294D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 9 page(s) / 356K

Publishing Venue

IBM

Related People

Mirza, JH: AUTHOR

Abstract

This article describes a method that reduces the cache coherence penalty associated with private caches in multiprocessor systems. The method differs from previous methods and techniques in that it greatly reduces the instances when a cross interrogate (XI) check has to be made by the processors in the system. This reduces the cache cycles that are non-productively usurped by the XI mechanism. Better system performance is thus obtained by using the cache more efficiently.

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Reduction of Cache Coherence Traffic in MP Systems Via Large Block Authority

       This article describes a method that reduces the cache
coherence penalty associated with private caches in multiprocessor
systems.  The method differs from previous methods and techniques in
that it greatly reduces the instances when a cross interrogate (XI)
check has to be made by the processors in the system.  This reduces
the cache cycles that are non-productively usurped by the XI
mechanism.  Better system performance is thus obtained by using the
cache more efficiently.

      Large modern computer systems are multiprocessor (MP) systems;
they have several independent processors that share a large main
memory.  The main memory, by nature of its being shared by all the
processors, tends to be further away from the processors (in cycles)
than it would be in a uniprocessor system.  Each processor may
therefore have one or more caches to minimize the apparent latency to
the shared memory.

      With multiple private caches in the system, it becomes
necessary to provide a mechanism that ensures multicache consistency.
This means that if a particular line resides in several caches, it
will be the same in all of them.  If a processor changes a line, the
latest copy of that line must be made available to any other cache
when the corresponding processor makes its next access to that line.
In other words, cache coherence must be guaranteed so that at any
given time, there is only one view of the data as seen by all the
processors.

      Several solutions exist and/or have been proposed for
maintaining cache coherence (*).

      One of the more widely used schemes is based on the idea of
cross- interrogating caches to invalidate lines from a cache if it no
longer contains the most recent value.  In its more sophisticated
form, it works as follows:
      Whenever a processor needs a line, it requests it with
Read-Only (RO) or Exclusive (EX) authority.  A line that is held RO
by a processor may only be read by the processor; it may not be
changed.  Multiple processors may hold the same line with RO
authority.  A line that is held EX by a processor may be both read
and modified by that processor.  The cache coherence mechanism
ensures that a line with EX authority exists in, at most, one cache
at any time.
      When a processor has a cache miss and requests a line RO, the
cache coherence mechanism first does a cross-interrogation (XI)
operation.  It broadcasts a request to all other processors to check
their cache directories for the line, and to demote the line to RO
authority if it exists.  The line is then granted to the requesting
processor with RO status.
      When a processor has a cache miss and requests a line EX, the
cache coherence mechanism does an XI operation to all other
processors to invalidate the requested line if it exists in those
caches.  The line is then granted to the requesting processor wit...