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Biased Random Pattern Test Generation

IP.com Disclosure Number: IPCOM000101296D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 82K

Publishing Venue

IBM

Related People

Koenemann, B: AUTHOR

Abstract

The test coverage achievable with simple equi-probably pseudo-random patterns is limited by the inability to control the patterns towards specific value combinations required for testing certain faults. The idea of the proposed new concept is to use inversion levels between the SRLs in the LSSD scan strings to associate some pattern biasing information with each SRL in an LSSD structure. The pattern source is a built-in, modified pseudo-random pattern generator to produce bit pattern sequences with a uniform 1-probability, p.

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Biased Random Pattern Test Generation

       The test coverage achievable with simple equi-probably
pseudo-random patterns is limited by the inability to control the
patterns towards specific value combinations required for testing
certain faults.  The idea of the proposed new concept is to use
inversion levels between the SRLs in the LSSD scan strings to
associate some pattern biasing information with each SRL in an LSSD
structure.  The pattern source is a built-in, modified pseudo-random
pattern generator to produce bit pattern sequences with a uniform
1-probability, p.

      If a bit with 1-probability p is inverted, then the resulting
1-probability becomes 1-p.  The figure illustrates how inversions in
an LSSD scan string thus influence the 1-probabilities in the SRLs (a
sequence with 1-probability p is shifted into the scan string).

      For p = 1/2, all SRL values have a uniform 1-probability of
1/2.  Different values of p, however, bias towards patterns 10011 (p
larger than 1/2) or 01100 (p smaller than 1/2).

      Only one bias pattern can be programmed into the structure as
proposed.  Selecting this pattern is equivalent to finding the
initial weight set for Weighted Random Patterns (WRPs) (1).  The
overall effectiveness depends on how many fault tests differ from the
bias pattern in only a few bit positions.  The success of the WRP
scheme indicates that such "clustering" of test patterns actually
occurs in real hardware.

      A fault test pattern is characterized by how many bits must
have specific values (fan-in).  These values differ from the bias
pattern in some bit positions (conflicts). For fan-in=f and
conflicts=c, f-c bits are properly biased while c bits are biased
wrong.  The probability that a single biased pattern achieves the
test is, thus, given by:
(1)  pdet(p) = p**(f-c) * (1-p)**c. This formula shows that the
optimal biasing parameter p depends for fault detection depends on
the number of conflicts: to resolve more conflicts is more difficult
and requires weaker biasing (p closer to 1/2).

      To cover a wide range of fan-ins and conflicts, the test can be
applied in sec...