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Control And Sequencing of Multiple Parallel Data Processors

IP.com Disclosure Number: IPCOM000101302D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 90K

Publishing Venue

IBM

Related People

Maclean, NH: AUTHOR [+3]

Abstract

Control and verification of the splitting and merging of a data stream between two data buses or channels through multiple parallel data processors (DPs) requires certain control hardware. Redundant control hardware verifies control of multiplexing and demultiplexing of the data streams for ensuring data integrity. Event counters in each data processor (DP) control and verify splitting and merging the respective data streams. This arrangement eliminates separate multiplexer/demul- tiplexer controls on each interface while verifying the control of multiplexing and demultiplexing of the data streams on both interfaces.

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Control And Sequencing of Multiple Parallel Data Processors

       Control and verification of the splitting and merging of
a data stream between two data buses or channels through multiple
parallel data processors (DPs) requires certain control hardware.
Redundant control hardware verifies control of multiplexing and
demultiplexing of the data streams for ensuring data integrity.
Event counters in each data processor (DP) control and verify
splitting and merging the respective data streams.  This arrangement
eliminates separate multiplexer/demul- tiplexer controls on each
interface while verifying the control of multiplexing and
demultiplexing of the data streams on both interfaces.

      The total number of parallel DPs and their respective position
in the system are defined to each Data Processor (DP).  An incoming
Data Stream (DS) on bus A is blocked into packets (packets fit into
an "A" buffer of each DP) so that each DP can receive one packet, and
then process this packet while the next DP in line receives the next
packet.  This procedure continues in a round-robin manner, until the
entire DS has been received. The Processed Packets (PPs) are stored
into "B" buffer in the respective DPs and the output of "B" buffer is
sent to B bus in the same order that the DS was received; this
maintains the original data sequence.

      Referring to Fig. 1, initially, the DP designated as DP/ has
control of the A bus and activates the appropriate Master Out (MOUT)
output until it has received the first packet.  Then, DP/ deactivates
its MOUT output and the DP designated as DP1 takes control of A bus
and activates its MOUT output until it has received the second
packet, at which time it deactivates its MOUT output.  This process
continues until DPn-1 has received its packet; then DP/ again takes
control and the whole se...