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Quick Polling Method for Related Auto-Clear Registers

IP.com Disclosure Number: IPCOM000101310D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Hardell, WR: AUTHOR [+3]

Abstract

Provides a means to quickly poll a group of related clear-on-read registers while keeping the data from the registers in sync with each other. This method requires the ability to poll one register in a fast non- clear mode to check the status of a group of registers. The resistors can be read in the normal clear-on-read mode by reading the slow register first and storing the other registers in shadow latches, and then reading the value of the other registers from the shadow latches.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 68% of the total text.

Quick Polling Method for Related Auto-Clear Registers

       Provides a means to quickly poll a group of related
clear-on-read registers while keeping the data from the registers in
sync with each other.  This method requires the ability to poll one
register in a fast non- clear mode to check the status of a group of
registers.  The resistors can be read in the normal clear-on-read
mode by reading the slow register first and storing the other
registers in shadow latches, and then reading the value of the other
registers from the shadow latches.

      For example, consider a system with three registers to indicate
single-bit errors in memory.  The registers are: Single Bit Status
Register (SBSR), Single Bit Address Register (SBAR) and Single Bit
Syndrome/Signature Register (SBSSR).  The SBSSR and SBSR are
clear-on- read registers. It is quick to read from the SBSR and the
SBAR because these registers are in the chip that controls I/O reads.
Assume that it is slow to read from the SBSSR because the SBSSR is in
a different chip than the SBSR and SBAR.  Also, the I/O control unit
must arbitrate for a shared bus to read the SBSSR.

      In this method, there is a state machine to control the reading
of the registers (see Figure 1).  In the initial state, this state
machine allows reading (polling) of the SBSR without clearing it.  If
software finds a single-bit error flagged in the SBSR, it will jump
to the error-handling routine.  Then software will read...