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Circuits for Transmitting And Receiving Characters Sent MSB or LSB First by Variable Number of Bits

IP.com Disclosure Number: IPCOM000101315D
Original Publication Date: 1990-Jul-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 5 page(s) / 148K

Publishing Venue

IBM

Related People

Caillet, B: AUTHOR [+2]

Abstract

Disclosed are two circuits to transmit from a storage, or receive in a storage, series of bytes sliced in variable bit numbers (0 to 9) and ordered LSB or MSB first, where MSB and LSB mean Most Significant Bit and Least Significant Bit, respectively.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Circuits for Transmitting And Receiving Characters Sent MSB or LSB First by Variable Number of Bits

       Disclosed are two circuits to transmit from a storage, or
receive in a storage, series of bytes sliced in variable bit numbers
(0 to 9) and ordered LSB or MSB first, where MSB and LSB mean Most
Significant Bit and Least Significant Bit, respectively.

      The transmission circuit is shown in Figs. 1 and 2.

      Two characters CN and CN+1 are read from a storage 1 at
consecutive addresses N and N+1. They are stored in a 16-bit buffer 3
through a multiplexer 2: if bytes are sent MSB first, they are loaded
as is; if they are sent LSB first, they are bit-to-bit reversed. The
16-bit buffer is then sliced according to a given "WIDTH" value, the
corresponding bits being sent through a selector 4. If bytes are sent
MSB first, they are selected as is; if they are sent LSB first, they
are bit-to- bit reversed.

      A control circuit 5 handles all the command lines as detailed
hereafter.
      The flow is schematically described in Fig. 1.
      Fig. 2 shows the details of the control circuit 5.

      A 4-bit register 6 contains the position of the "FIRST" bit to
be sent during the transfer in the 16-bit register 3 (bit 0 at
start).

      Three adders 7 compute the position of the "LAST" bit to be
sent and the "NEW" position of the first bit to send at the next
transfer using the given current "SLICE WIDTH" value.

      A comparator 8 checks if the "NEW" first bit belongs to
Character N+1. If not, the "NEW" value is stored in the 4-bit
register 6 when all bits have been transmitted in the current
transfer. If yes, the "NEW" value MINUS 8 is loaded in the 4-bit
registers 6, the storage address value N is incremented by 1 by adder
9 and two new characters (i.e., CN+1 and CN+2) are loaded in the
16-bit buffer.

      The bits to be transmitted are selected in the 16-bit buffer
according to the following formula:
      transmit Bit j where FIRST & j & FIRST+WIDTH-1
      The receive circuit is shown in Figs. 3 and 4.

      A number of bits (given by a "COUNT" value) is received and
stored in a 16-bit buffer 3 throug...