Browse Prior Art Database

Extended Copy Page Mode for Dynamic Random-Access Memories

IP.com Disclosure Number: IPCOM000101349D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 113K

Publishing Venue

IBM

Related People

Fifield, JA: AUTHOR [+4]

Abstract

By improving data transfer rates within memory arrays through the utilization of multibit copies, quick replication of test patterns, efficient transfer of blocks of stored memory, and data security erase features are facilitated.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Extended Copy Page Mode for Dynamic Random-Access Memories

       By improving data transfer rates within memory arrays
through the utilization of multibit copies, quick replication of test
patterns, efficient transfer of blocks of stored memory, and data
security erase features are facilitated.

      Current methods of data transfer are limited in address space
on an I/O by the physical length of a bit line. Changes in address
beyond the bit line boundary are not allowed. Since the register that
holds the data is not the sense amplifier in the new approach, any
page can be copied to any other page within the I/O. As with previous
methods, no transfer can occur from one I/O to another.

      Page copy is currently performed by suppressing array restore
and leaving the sense amplifiers set after the first read cycle. Data
is copied from the word line which was first read to all other
activated word lines while the restore is disabled. In order to
change the copy data, a disable of the function must occur to restore
the array, followed by an enable of the copy function. The new method
allows updates in the copy data to occur with each read cycle and
copies for each write cycle, as determined by the write (W) pin at
each column enable (CE) time.

      Referring to Fig. 1, a read, which loads the copy data into a
register gated by a precharge NOR exclusive OR (PCNX) line, can be
followed by any number of write cycles which copy data to the page
address of the write cycle. Actual writing to the register and hence
the array is disabled by the page copy not (PGECOPYN) signal while
the feature is activated. The PGECOPYN signal is an input to the I/O
and control block, and disable of the write occurs at this point.
Read cycles still output data to the off-chip drivers (OCDs). The
PCNX circuit consists of control logic which generates PCNX upon the
fall of array restore not (ARN) and resets it with static RAM valid
(SRV) or row address select enable (RE). The PCNX pulse is finally
enabled by the stop phase not (STOPFN) line generated from the copy
page circuit. I/O circuits provide a path from the SRAM registers to
and from the I/O pads.

      Use of the feature for data security requires the dedication of
one page of memory (128 bits per I/O in the example) for loading the
clear da...