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Long-Term, Battery-Backed Data Retention for Static Random-Access Memory Systems

IP.com Disclosure Number: IPCOM000101354D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Berger, ER: AUTHOR [+2]

Abstract

Disclosed is a circuit which solves the problem of accumulated soft errors leading to uncorrectable data retrieval when large Static Random-Access Memory (SRAM) arrays remain on battery power for long periods.

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Long-Term, Battery-Backed Data Retention for Static Random-Access Memory Systems

       Disclosed is a circuit which solves the problem of
accumulated soft errors leading to uncorrectable data retrieval when
large Static Random-Access Memory (SRAM) arrays remain on battery
power for long periods.

      A periodic (once per month) scrub of the array, shown in Fig.
1, will scrub all single bit errors accumulated and require only
approximately 2 watts/sec of energy.  Typical primary batteries
(i.e., Lithium Thionyl Chloride (LTC)) supply approximately 1 amp/hr
at 3 volts.  This type of primary battery could supply power to scrub
the array approximately 3600 times with no wear-out for the storage
life of the battery.  The storage life of LTC batteries approaches 10
years.

      The circuit shown in Fig. 1 operates from either prime power +5
VDC or a battery.  Battery power supplies 3 volts to retain the
memory of the SRAMS when the +5 V primary power supply is not
available.  Four LTC cells, stacked in series, generate a 12-volt
power source, which trickle charges a .25 farad capacitor.  The .25
farad capacitor utilizes electric double layer capacitors to obtain
the high energy density required for the periodic scrub operation.

      The control circuit which includes a CMOS Timer and switch is
powered by the battery and uses a real-time clock to provide +5 V to
the Memory Array and Error Detection and Correction (EDAC) Logic
approximately once per mon...