Browse Prior Art Database

Fast Dual-Port Memory With Standard Off-The-Shelf MSI Logic

IP.com Disclosure Number: IPCOM000101362D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 5 page(s) / 154K

Publishing Venue

IBM

Related People

Purrington, CL: AUTHOR

Abstract

Disclosed is a design for a Fast/True Dual-Port Memory (FTDPM) architecture that can be implemented with standard off-the-shelf components. The FTDPM provides variable amounts of fast Dual-Port Memory (DPM) with minimal hardware and without many of the limitations of other designs. The design is centered around a simple register interface and a fast state machine, implemented with fast PROMS and edge-triggered registers, that performs the required memory bus arbitrations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Fast Dual-Port Memory With Standard Off-The-Shelf MSI Logic

       Disclosed is a design for a Fast/True Dual-Port Memory
(FTDPM) architecture that can be implemented with standard
off-the-shelf components.  The FTDPM provides variable amounts of
fast Dual-Port Memory (DPM) with minimal hardware and without many of
the limitations of other designs.  The design is centered around a
simple register interface and a fast state machine, implemented with
fast PROMS and edge-triggered registers, that performs the required
memory bus arbitrations.

      DPM is a type of random-access storage that can be accessed
from two ports (two devices).  This type of memory is sometimes used
to pass data and messages between processors or smart I/O devices.

      The described DPM design requires neither software handshaking
or memory wait cycles.  This design has a worst-case read or write
cycle time of 500 nanoseconds (ns). Depending on the state of the
other port, a read or write cycle may range from 200 ns to 500 ns.
With additional circuitry this can be reduced to 100 ns-300 ns.

      The primary objective of the DPM was to provide Port 1 with the
capability of writing data to external random-access memory (RAM) at
a 840 ns rate while allowing the other port read and write capability
at the same 840 ns rate.

      The DPM design must:
1.   accept asynchronous memory requests from either port;
2.   contain 4K-16K bytes of RAM;
3.   be capable of residing on less than 16 square inches of
     card space; and
4.   be designed using all off-the-shelf components.

      The objective was accomplished by temporarily latching the port
address and data into registers and allowing some control circuitry
to perform the actual read or write operation on memory.  See Fig. 1.

      This design allows two devices access to the same RAM without
compromising performance.  Unlike some implementations of "Dual-Port
RAM," this does not require software handshaking or force a device to
wait for memory access.

      The data flow section consists of registers and RAM. The
registers (port 1 registers and port 2 registers) are used to isolate
the memory from the two-device ports and to temporarily store data in
and out of memory.  These port registers are under the control of the
bus arbiter.  The type of components used in the Data Flow Circuit
are eight-bit, edge-triggered registers, two-bit latches and 70 ns 16
Kx1 RAMS.  Fig. 3 shows a high level illustration of a DPM that
supports reads and writes on both ports.

      The "Sequential State Machine", or "Arbiter", is made up of
bipolar PROMS and edge-triggered registers.  It can execute five
sequences of operations:  Port 1 Read, Port 1 Write, Port 2 Write,
Port 2 Read Operation and Poll/Idle. Continued

      The Arbiter controls the data flow between the two-port
register groups and RAM.  The design consists of two bipolar 512 x 8
PROMS and two eight-b...