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Browse Prior Art Database

Simultaneous Formation of Glass And Silicon Trenches

IP.com Disclosure Number: IPCOM000101364D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Barbee, SG: AUTHOR [+4]

Abstract

Proposed is a process to simultaneously form narrow oxide-filled trenches and wide epitaxial silicon-filled trenches in semiconductor device fabrication. The process is useful in situations where the semiconductor substrate cannot be contacted from its backside.

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This is the abbreviated version, containing approximately 100% of the total text.

Simultaneous Formation of Glass And Silicon Trenches

       Proposed is a process to simultaneously form narrow
oxide-filled trenches and wide epitaxial silicon-filled trenches in
semiconductor device fabrication.  The process is useful in
situations where the semiconductor substrate cannot be contacted from
its backside.

      In the process, a thin thermal SiO2 layer 1 (Fig. 1) is formed
along with a Si3N4 layer 2 as the liner for the walls of the narrow
and wide trenches.  A chemical vapor deposition (CVD) SiO2 3 is laid
down and a boron ion channel implant 4 is performed if the CVD
deposition does not contain any boron oxide.

      After the channel implant, the narrow trench is completely
filled with CVD glass 5 (Fig. 2) while the wide trench is lined with
a thick CVD glass sidewall 6.  A timed CF4 reactive ion etch (RIE)
provides the structure in Fig. 3 with the fill of the narrow trench
having a slightly reduced trench fill height.  The deposition of
selective epitaxial silicon 7 (Fig. 4) is next done in only the wide
trench area, followed by planarization.

      For device cell layout, the narrow trench 8 (Fig. 5),
previously filled with CVD glass, may be covered by extrinsic base
polysilicon without the possibility of polysilicon-to-trench fill
shorts while the substrate contact 9 is formed in a wide trench width
area 10.