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Method for measuring frequency reponse of nanoscale transistors

IP.com Disclosure Number: IPCOM000101367D
Original Publication Date: 2005-Mar-16
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 89K

Publishing Venue



Disclosed is a novel structure and method of fabricating a carbon nanotube field-effect transistor (CNFET) having very low gate-drain parasitic capacitance. The structures enable the measurement of the frequency response of CNFETs and similar nanoscale transistors well into the GHz regime, far exceeding the highest frequencies at which CNFET measurements have been reported, and additionally enables low capacitance interconnect wiring for fabricating circuits with CNFETs. The proposed structure also provides a new paradigm for fabricating high frequency circuits using carbon nanotube FETs and other nanoscale transistors.

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Method for measuring frequency reponse of nanoscale transistors

  Recent progress in engineering carbon nanotube field-effect transistors (CNFETs) has resulted in CNFETs with excellent DC characteristics making them promising candidates for future nanoelectronics technologies. The excellent transport properties in carbon nanotubes, attributed in part to the suppressed carrier scattering rates in one-dimensional (1-D) systems results in high mobilities and long scattering lengths (on the order of several microns. Additionally, identical energy dispersion curves for the conduction and valence bands imply similar electron and hole effective masses and results in high performance for both n and p -type CNFETs. This is an advantage over conventional CMOS where the higher effective mass of holes compared to electrons degrades p -MOSFET performance compared to n -MOSFETs. However, despite the tremendous interest in CNFET devices for future circuit applications, there have been few studies of the AC performance of CNFETs and no direct measurement of their switching properties for frequencies in excess of a few hundred MHz, and no demonstrations of high frequency circuits made of interconnected CNFETs

  The measurement of the frequency response of such narrow width devices cannot use conventional methods. S-parameter measurements with a network analyzer are not possible because the parasitic probe pad capacitanceis much larger than the intrinsic device capacitance and because of the small magnitude of the signal generated by a single tube CNFET in a 50 Ohm instrument. Since S-parameter measurements use the small signal swing, the measured signal is too small even for CNFETs with maximum drain currents of the order of 10µA. Similarly, transit time measurements with a high bandwidth system are not possible because the signal is far below the measurement noise of oscilloscopes.





Insulating Substrate

Fig. 1


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  For typical CNFETs fabricated in the conventional manner where the origin and the direction of CNFETs are poorly defined relatively large source/drain pads are employed to ensure contact to a carbon nanotube and a large capacitance exists in the overlap region of the gate/drain which overwhelms the intrinsic gate-drain capacitance of the CNFET. A typical layout is shown in Fig. 1. This layout has a parasitic gate-to-drain overlap capacitance on the order of a few tens of femtofarads, limiting the measured frequency response to a few hundred MHz.

  The first step in realizing a low parasitic capacitance CNFET measurement structure involves defini...