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Browse Prior Art Database

Method of Eliminating Discharge in Cmos Dynamic Domino Chain

IP.com Disclosure Number: IPCOM000101368D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 83K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR [+2]

Abstract

A technique is described to eliminate discharge problems associated with clocked CMOS dynamic domino chain circuitry.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Method of Eliminating Discharge in Cmos Dynamic Domino Chain

       A technique is described to eliminate discharge problems
associated with clocked CMOS dynamic domino chain circuitry.

      In prior art, constraints have been imposed (*) in the
formation of a domino chain to ensure that all the inputs to the
domino chain are "domino-gate" type of signals.  For example, signals
are at ground potential during precharge.  If not, a precharge node
may leak away its charges, resulting in propagating an incorrect
signal along the domino chain.  The concept described herein
implements a logic transformation and a circuit implementation that
eliminates the problem of non-domino gate (NDG) in the CMOS circuits.

      A logic transformation, referred to as "Split, Invert and
Merge" (SIM), is applied to a real expression derived in generating
the 'Sum' term of a 32-bit arithmetic logic unit (ALU).  The 'Sum'
circuit of the ALU and its related timing diagram are shown in Figs.
1 and 2, respectively. There exist two discharge paths, as shown in
Fig. 3, namely

                            (Image Omitted)

          F = f1 + f2
          f1 = pcw +pcx
          f2 = --y+--z

      The original logic equation F, is split into its constituent
sub-functions f1 and f2.  The NDG problem in f2 can be eliminated by
performing an invert transform, as shown in Fig. 4.  The result of
this _ transformation, i.e., g-functi...