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Data Width And Format Conversion Subsystem for a Graphics Coprocessor

IP.com Disclosure Number: IPCOM000101373D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 8 page(s) / 315K

Publishing Venue

IBM

Related People

Johnson, LE: AUTHOR [+4]

Abstract

In graphics rasterization it is desirable to maintain near 100% utilization of the frame buffer memory bandwidth. Our invention supports the achievement of that goal during BitBlt format conversion using interlocked state machines and closely coupled data communication in order to provide overlapped parallel execution. In addition, this subsystem provides a FIFO (first-in, first-out) buffered interface to a general purpose processor that can transfer data structures to and from this subsystem in parallel with execution.

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Data Width And Format Conversion Subsystem for a Graphics Coprocessor

       In graphics rasterization it is desirable to maintain
near 100% utilization of the frame buffer memory bandwidth. Our
invention supports the achievement of that goal during BitBlt format
conversion using interlocked state machines and closely coupled data
communication in order to provide overlapped parallel execution. In
addition, this subsystem provides a FIFO (first-in, first-out)
buffered interface to a general purpose processor that can transfer
data structures to and from this subsystem in parallel with
execution.

      Introduction: Figure 1 shows a typical workstation graphics
subsystem.  A Front End Graphics Processor 100 performs graphics
processing tasks such as transformation, clipping, and lighting
calculations.  Commands are then passed to a Rasterization Processor
and Display Controller 110.  The rasterization processor controls
three buffers: a frame buffer 120 (which may be double buffered)
typically of 24-bits precision (8 each in Red, Green, and Blue); a
Z-buffer 130 (typically of 24 bits precision corresponding to the
depth at every pixel); and an attribute buffer 140 containing
information about the pixels in the buffer (such as which window they
belong to, whether they are protected from being written to, etc.).
The frame buffer 120 is composed of video RAM allowing fast access
for display refresh purposes. The video RAM serial ports feed a
RAMDAC 150 which generates the video data stream for a CRT display.

      Description: The role of the Rasterization Processor 110 is to
perform the "inner loop" of the processing of the graphics commands.
The inner loop typically consists of generating the pixels along a
line (for line drawing), copying from one area of the screen (frame
buffer) to another and performing a logical or arithmetic function
between the two areas (for BitBlt), or filling a triangular-shaped
area with properly shaded pixels after performing a depth comparison
test (Z-buffered Gouraud shaded triangles).  The movement of data
between the frame buffer and the host processor is called an External
BitBlt. The goal of the Rasterization Processor 110 is to utilize
100% of the available bandwidth into frame buffer 120 for updating
pixels.  This holds true whether the graphics processor is
rasterizing triangles, lines, or performing BitBlts.  The challenge
is to not only be able to process the input command (triangle, line,
or Blit) fast enough but also to provide an interface to the system
such that subsequent commands can be performed without any "gaps" in
the memory utilization.

      Figure 2 is a more detailed block diagram of the Rasterization
Processor and Display Controller 110 of Figure 1.  There is an Input
Interface functional block 200 which provides the interface between
the front end graphics processor 100 and the internal registers of
the Rasterization Processor's functional blocks.

      The...