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Direct Capacitor Attachment for Logic Chips

IP.com Disclosure Number: IPCOM000101407D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Gruber, HE: AUTHOR [+3]

Abstract

The approach described in this article allows very high frequency decoupling on chip level by capacitors which are directly attached to the active chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 93% of the total text.

Direct Capacitor Attachment for Logic Chips

       The approach described in this article allows very high
frequency decoupling on chip level by capacitors which are directly
attached to the active chip.

      As a result of this attachment, the charge of the capacitors
only passes the C4 connections and is available on the chip for
checking voltage noise.  This applies to MCMs and SCMs (multi- and
single-chip modules) as well as to PGA (pin grid array) modules.  In
the case of MCMs and SCMs, the capacitor is soldered directly to the
VLSI chip.  The capacitor used for this purpose may be the same as
that employed for MCM/SCM decoupling.

      In state-of-the-art applications, the charge first passes the
C4s to the MCM, then the MCM power meshes, and finally the C4s from
the MCM to the chip, so that the total inductance is much higher than
for the direct capacitor attachment described in this article.

      The areas chosen for the capacitors are the four corners of the
chip (Figs. 1 and 2).  Some new C4 pads are necessary for holding the
capacitors.  Normally, the distance restrictions of the neutral point
do not allow functional C4 pads to be positioned at the corners (C4
stress).  If the chip slightly changes its width in response to
increasing temperatures, the capacitor fully participates in this
movement.

      Known PGA packages are not suitable for on-module decoupling.
Fig. 3 shows how to integrate capacitors for PGA modules.  The cav...