Browse Prior Art Database

Micro Channel Bus Latch Card

IP.com Disclosure Number: IPCOM000101429D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 7 page(s) / 252K

Publishing Venue

IBM

Related People

Petroski, MP: AUTHOR

Abstract

This article describes a bus latch card that plugs into a MICRO CHANNEL* and which is utilized as a tool to aid in the debugging of apparently "dead" personal computer (PC) systems. Also, it can act as an output device for displayless systems.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 38% of the total text.

Micro Channel Bus Latch Card

       This article describes a bus latch card that plugs into a
MICRO CHANNEL* and which is utilized as a tool to aid in the
debugging of apparently "dead" personal computer (PC) systems.  Also,
it can act as an output device for displayless systems.

      In this disclosure A0-A19, D0-D7, S1, S0, CMD and M/I0 are
MICRO CHANNEL signals taken from personal computer (PC) system bus
connectors.

      As power on self-test (POST) is executed in a PC system, a
two-digit hex number is written to port 03BC. This two-digit number
(referred to as the "checkpoint") indicates the start of a particular
test in POST.  The latch card monitors the bus and displays what is
written to port 03BC.  If the PC hangs during POST, the
identification of the last test it entered is displayed.  On the
manufacturing floor, the checkpoints are used with the manufacturing
code to accurately identify failing commodities.

      In addition to the two-digit checkpoint, the latch card also
displays what is written into memory locations B0002, B0004, B0006,
and B0008.  These memory locations contain the memory-count digits
that appear on the top left of the monitor during a normal POST.
These additional displays help find memory faults on the
manufacturing line.

      The discussion of the circuitry on the card is broken into the
checkpoint section and the memory-count section. To keep chip count
low, certain overlaps in the circuitry are necessary.  The checkpoint
section is shown in Figs. 1A, 1B, 1C, and 1D.

      The decode of port address of 003BC starts with five 74LS42
hex- to-decimal decoders.  These modules present an active low on one
of ten output lines corresponding to the hex address presented.  The
order of the address lines presented to the decoder modules U1, U2,
U3, U4, and U5 may not seem apparent.  The addresses are arranged so
that the hex data presented to the decoder modules always has single-
digit decimal equivalents.  A further rearrangement is necessary so
that the memory addresses (B0002, B0004, B0006, and B0008) also can
be decoded using the same five decoders.

      The active low outputs (from 74LS42s), corresponding to the
correct address 003BC are fed into the chain of NOR gates U8A through
C, U9A and B (Figs. 1A and 1B).  The length of the chain and the
trend towards higher system speeds necessitate that the modules be
the "F" version.  The final stage of the NOR chain expects a signal
indicating that the address written to was a port address.  If it is,
a 74LS374 octal latch U15 (Fig. 1D) is triggered to latch the data
byte present on the bus.  The latched data is presented to the TIL311
displays.

      Module U6 (Fig. 1B) is used to decode the PC bus control
signals S1, S0, CMD, AND M/IO.  A WRITE is indicated by the line SO
being low and S1 being high.  The M/IO line determines if the
operation is directed towards memory or port devices (a low to M/IO
indi...