Browse Prior Art Database

Hardware Simulation Accelerator Model for AETs

IP.com Disclosure Number: IPCOM000101436D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Hoffman, H: AUTHOR [+3]

Abstract

Disclosed is a method for arranging a hardware simulation accelerator model for gathering AET (All Events Trace) information.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 94% of the total text.

Hardware Simulation Accelerator Model for AETs

       Disclosed is a method for arranging a hardware simulation
accelerator model for gathering AET (All Events Trace) information.

      To allow nets to be logged on a hardware simulation
accelerator, a number of commands must be added to the accelerator
model.  First of all, a check to see if net tracing is off must be
added.  If net tracing is off, a branch back to the beginning of the
model will be executed. If net tracing is on (AET ON), then the
following commands will be executed.  This allows AET gathering by
the hardware accelerator, which is spread across multiple trace
commands, to be easily enabled or disabled by setting a single bit in
the accelerator rather than by enabling or disabling all the trace
commands.  See the figure.

      A set of commands that will configure the accelerator as an AET
gatherer is added.  These commands are called the AET header
commands.

      The commands which tell the hardware simulation accelerator
which nets to trace are added next.  A trace command is used to
collect data during a simulation and send that data back to the host.
All nodes which are included in a trace command will be logged to an
AET file at the end of each cycle of simulation.

      Finally, a branch command (to beginning of model) is added.
After executing this command, processing for the next cycle begins.
At this point, tracing can be turned off, a new set of nets and
arrays can...