Browse Prior Art Database

External Burst-Mode FIFO for Non-Burst Diskette Controller

IP.com Disclosure Number: IPCOM000101437D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 99K

Publishing Venue

IBM

Related People

Dean, ME: AUTHOR [+3]

Abstract

This article describes a mechanism for use in a personal computer system that can eliminate MICRO CHANNEL* diskette direct memory access (DMA) overrun errors by the addition of a buffer to the diskette controller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

External Burst-Mode FIFO for Non-Burst Diskette Controller

       This article describes a mechanism for use in a personal
computer system that can eliminate MICRO CHANNEL* diskette direct
memory access (DMA) overrun errors by the addition of a buffer to the
diskette controller.

      The floppy disk controller (FDC) chips currently used are non-
buffered devices, which means that data transfers between the host
system and the FDC must occur within fixed time constraints
determined by the serial data rate recorded on the media.  If the
host system cannot service the FDC DMA requests within these time
constraints, then DMA overrun errors will occur.   These errors are
undesirable because the attempted operation must be repeated
(retried).  In MICRO CHANNEL architecture implementation these
overruns can occur in the following situations:
1.   When heavy DMA traffic occurs on two or more arbitration levels
having higher priority than the diskette arbitration level.
2.   When the CPU performs 16- or 32-bit string moves to video RAM.

      This problem is solved by adding a data buffering mechanism
between the FDC and DMA controller, as shown in block diagram in Fig.
1.  The data buffer permits burst-mode transfers between itself and
the DMA controller, and single-byte transfers between itself and the
FDC.  This data buffer is distinguished from ordinary first-in,
first-out (FIFO) implementations by its unique application and by the
design of its control logic, which is described below.

      Two independent algorithmic state machines are used for data
buffer control, which allows diskette and DMA transfers to occur
independently of each other.  Thus, overlapping, non-overlapping, and
simultaneous transfers are permitted. The host interface state
machine drives the control signals necessary to perform burst
transfers between the system and FIFO.  The floppy interface state
machine then generates the DMA acknowledge (FDCDACK) a...