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Fixed-Parity Pseudorandom Number Generator

IP.com Disclosure Number: IPCOM000101440D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

McAnney, WH: AUTHOR

Abstract

Disclosed is a circuit for generating fixed-parity pseudorandom numbers by modifying a linear feedback shift register (LFSR). An example is shown in Fig. 1, in which the block marked SRL is an LSSD shift register latch and XOR is a modulo-2 adder. Fig. 2 lists the two cycles of the fixed-parity generator of Fig. 1.

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Fixed-Parity Pseudorandom Number Generator

       Disclosed is a circuit for generating fixed-parity
pseudorandom numbers by modifying a linear feedback shift register
(LFSR).  An example is shown in Fig. 1, in which the block marked SRL
is an LSSD shift register latch and XOR is a modulo-2 adder.  Fig. 2
lists the two cycles of the fixed-parity generator of Fig. 1.

      In an n-stage fixed-parity generator, the first n - 1 stages
must be an LFSR that implements a primitive polynomial.  The XOR of
the nth stage (SRL 5 in Fig. 1) must be driven by all of the
feedbacks of the LFSR except that from its (n - 1)th stage.  The AND
gate must be driven by the complements of the first n - 2 stages of
the LFSR.  For an example other than a primitive trinomial, see the
nine-stage fixed- parity generator of Fig. 3 which uses the primitive
polynomial x8 + x6 + x5 +x + 1.

      The nth stage of the class of circuits described by Figs. 1 and
3 generates a parity check (either even or odd) across all possible
2n-1 words from the first n - 1 stages of the generator, as can be
seen from the list of Fig. 2. The words in the even parity list have
Hamming distances 2, as do those on the odd parity list.