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Technology Mapping Using Simulated Annealing

IP.com Disclosure Number: IPCOM000101442D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 40K

Publishing Venue

IBM

Related People

Gonsalves, GJ: AUTHOR

Abstract

A software product is described that uses simulated annealing (1) with a set of macro creation and macro expansion programs to synthesize a technology-dependent logic design from a functionally equivalent NAND or NOR representation.

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Technology Mapping Using Simulated Annealing

       A software product is described that uses simulated
annealing (1) with a set of macro creation and macro expansion
programs to synthesize a technology-dependent logic design from a
functionally equivalent NAND or NOR representation.

      The algorithm computes the change in the cost of the design
associated with the application of a macro creation or macro
expansion on a randomly selected technology independent primitive
logic block or a technology-dependent logic block, respectively.  The
cost change evaluates to infinity if a selected pattern cannot be
found in the logic surrounding the randomly selected block.  In all
other cases, changes in the projected cell count, the connections,
the total path delay, the critical path delay, and the power
dissipation represent the elements in the cost vector.  The procedure
performs the candidate transformation if the number produced by a
pseudo-random number generator exceeds the value returned by the
evaluation of the Metropolis function (2) with the computer cost
change.  This procedure is repeated a fixed number of times at
successively lower temperatures as determined by the annealing
schedule which can be adjusted in response to experimental results.

      The probabilistic algorithm produces a better member of the
sample space of technology-dependent logic designs and increases the
amount of automation of the translation task because it uses an
improved t...