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"Allocated Bits" for Machines With Vector Registers

IP.com Disclosure Number: IPCOM000101444D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 5 page(s) / 224K

Publishing Venue

IBM

Related People

Stanton, RJ: AUTHOR [+2]

Abstract

In many of today's supercomputers, vector registers are part of the architectural definition. These registers greatly increase the amount of machine state information which may be involved in the save/restore of a task switch. In either a save or restore on an IBM 3090/VF, the maximum number of pairs of vector registers involved is eight, where each pair contains 1024 bytes. In recognition of the potential save/ restore penalty associated with the vector registers, many machines have hardware-controlled mechanisms which attempt to track previous register use, i.e., "cleared", "not changed since last save", etc.

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"Allocated Bits" for Machines With Vector Registers

       In many of today's supercomputers, vector registers are
part of the architectural definition.  These registers greatly
increase the amount of machine state information which may be
involved in the save/restore of a task switch.  In either a save or
restore on an IBM 3090/VF, the maximum number of pairs of vector
registers involved is eight, where each pair contains 1024 bytes.  In
recognition of the potential save/ restore penalty associated with
the vector registers, many machines have hardware-controlled
mechanisms which attempt to track previous register use, i.e.,
"cleared", "not changed since last save", etc.  The inclusion of the
vector in-use and vector change bits (whose sole purpose is to reduce
the amount of "active" data) clearly indicates that it is considered
worthwhile to add small amounts of hardware if the save/restore
overhead for task switches can be reduced.

      Allocated Bits allow the compiler to pass information to the
hardware/operating system about future use of the vector register
contents.  This mechanism could 1) supersede a machine's current
mechanisms of tracking "active" vector data, 2) be used in
conjunction with the current mechanisms, or 3) be used by itself in
machines which do not currently have any mechanisms.  The Allocated
Bits are used to shadow the compiler's view of which vector registers
are allocated at any point of execution.  There is a one-to-one
relationship between an Allocated Bit and a vector register. (If used
in conjunction with the current mechanism in the IBM System/370
vector architecture, a give Allocated Bit would be associated with a
register pair, so as to be consistent with the definitions of the
in-use and vector change bits.)

      If used in conjunction with current IBM System/370 mechanisms,
two instructions would affect (or be affected) by the Allocated Bits:
DEALLOCATE VR and SAVE VR (in some implementations, RESTORE VR may
also set the Allocated Bits).  The DEALLOCATE VR instruction would
clear a specified set of Allocated Bits; the manner of specification
could be similar to that used by the CLEAR VR instruction in
specifying register pairs.  Instructions such as SAVE VR (and SAVE
CHANGED VR) would function similarly to the current IBM System/370
definitions; however, prior to the normal operation, any clear-valued
Allocated Bit would force the clearing of the associated register
(pair).  (Obviously, if used in conjunction with "in-use" bits,
registers known to be clear would not need to be re-cleared.)

      To illustrate the benefits of the proposed mechanism, it will
be discussed as an addition to the current hardware mechanisms
supported in the IBM 3090 Vector Facility.  The current vector
architecture includes three mechanisms which reduce the amount of
vector register data which is saved/restored during a task switch.
1.   The vector-control bit:  Bit 14 of control register 1...