Browse Prior Art Database

Sparse Matrix Modeling Technique for Memory Simulation

IP.com Disclosure Number: IPCOM000101445D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 26K

Publishing Venue

IBM

Related People

Hoffman, H: AUTHOR [+2]

Abstract

Disclosed is a method of providing large amounts of usable logic simulation memory by modeling the memory using the shared memory segments feature of AIX*.

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Sparse Matrix Modeling Technique for Memory Simulation

       Disclosed is a method of providing large amounts of
usable logic simulation memory by modeling the memory using the
shared memory segments feature of AIX*.

      Typical logic simulations may require large amounts of memory
to be available.  However, most simulations do not actually use all
the memory; instead, the simulations require memory from many
non-contiguous locations.  The sparse modeling technique takes
advantage of shared memory segments in AIX* to model this memory.
This technique provides several advantages.  Apparent array sizes of
up to 256-gigabytes may be modeled, even though the host machine may
have only a few megabytes of real memory.  No special software is
required for each dynamic allocation/usage.  The host computer may
have special-purpose hardware to speed up handling of shared
segments.  Memory is dynamically initialized to zero upon usage.
Additional software processes may access the memory for debugging or
tracing execution.
*  Trademark of IBM Corp.