Browse Prior Art Database

Dual-Rate Timer

IP.com Disclosure Number: IPCOM000101446D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Mizzi, JV: AUTHOR

Abstract

The objective of this circuit is to make the best use of a limited number of timing information bits by maintaining fine resolution for timing short durations while trading off resolution for long interval capability for long durations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 60% of the total text.

Dual-Rate Timer

       The objective of this circuit is to make the best use of
a limited number of timing information bits by maintaining fine
resolution for timing short durations while trading off resolution
for long interval capability for long durations.

      The logic diagram shows an implementation for a 16-bit
dual-rate timer.  The definitions and formulas below describe the
operation.
      BCT:      Basic Cycle Time
      BP:       Break Point, an integral power of 2
      MULT:     Multiplier, an integral power of 2
      COUNT:    The timing information bits
      IF COUNT   BP:
     Time = BCT X COUNT with resolution (uncertainty) = + BCT
      IF COUNT   BP:
           Time = (BCT X BP) + (COUNT - BP) X MULT X BCT
                with resolution = + BCT X MULT
      For example, suppose BCT = 50 nanoseconds
                           BP  = 4096 and MULT = 2048:
           Case 1:   COUNT = 3172
                     Time  = 50 nanoseconds X 3172 = 158,600
                             nanoseconds + 50 nanoseconds
           Case 2:   COUNT = 6344
            Time  = (50 nanoseconds X 4096) + (6344 - 4096) X
                             2048 X 50 nanoseconds
               = 230,400 microseconds + 102,400 nanosecond...