Browse Prior Art Database

Performance Enhancement for Multiprocessor Virtual Address Caches

IP.com Disclosure Number: IPCOM000101451D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 82K

Publishing Venue

IBM

Related People

Baylor, S: AUTHOR [+2]

Abstract

Disclosed is a modification of a multiprocessor virtual address cache design proposed by Goodman (*). The model system includes processors and associated private and/or shared memory modules and an interconnection network. The variant is designed to significantly improve the overall performance of the system by reducing the cost of servicing cache misses. The performance improvement is obtained by adding a minimal number of bits to the address header of requests traversing the interconnection network.

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Performance Enhancement for Multiprocessor Virtual Address Caches

       Disclosed is a modification of a multiprocessor virtual
address cache design proposed by Goodman (*).  The model system
includes processors and associated private and/or shared memory
modules and an interconnection network.  The variant is designed to
significantly improve the overall performance of the system by
reducing the cost of servicing cache misses.  The performance
improvement is obtained by adding a minimal number of bits to the
address header of requests traversing the interconnection network.

      Goodman's proposal maintains consistency across caches and
virtual address spaces.  It consists of the traditional data store
and two tag stores: one virtual (vStore) and one real (rStore) for
each line.  The vStore basically functions as a typical cache tag
store (servicing CPU requests and supplying data), whereas the rStore
functions as a snooping controller, accessed using real addresses
supplied by the network.  (Goodman's paper assumes a bus-based
interconnection network; however, this proposal may also be used in
multi-stage interconnection networks (MINs).)

      Both the virtual and physical addresses have the same page
offset; however, a variable number of additional (or EXT) bits from
the virtual and physical addresses are used to index the vStore and
rStore, respectively.  The number of additional bits depends on the
cache design parameters such as cache size, set-size, etc.  In
addition to the normal information located in the vStore, the EXT
bits of the line's corresponding real address (R-EXT) and the
location of that line within the set of the rStore entry are also
included.  This information serves as a pointer to the line's rStore
information and is used to determine the physical address when a
network access is required. Conversely, the corresponding vStore
pointer information is included in each rStore entry.

      There are some disadvantages to this proposal. Firs...