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Rotating Parity Checking Design That Allows a Large Number Of Registers to Be Checked With a Minimal Amount of Logic

IP.com Disclosure Number: IPCOM000101454D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 103K

Publishing Venue

IBM

Related People

Hardell, WR: AUTHOR [+2]

Abstract

In a processor there are a large number of registers that are used for configuration of the memory and I/O subsystems that need to be parity checked. All of these registers are written during the initial configuration of the system and will be rarely modified or read after that point. These registers need to be parity checked to ensure the reliability of the system. Adding a parity checker for each register would add too much additional logic to the system. A method was needed to check there registers without adding a parity checker for each one. This article describes a design that allows the registers to be periodically checked without adding a significant amount of logic to the design.

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This is the abbreviated version, containing approximately 52% of the total text.

Rotating Parity Checking Design That Allows a Large Number Of Registers to Be Checked With a Minimal Amount of Logic

       In a processor there are a large number of registers that
are used for configuration of the memory and I/O subsystems that need
to be parity checked.  All of these registers are written during the
initial configuration of the system and will be rarely modified or
read after that point.  These registers need to be parity checked to
ensure the reliability of the system.  Adding a parity checker for
each register would add too much additional logic to the system. A
method was needed to check there registers without adding a parity
checker for each one.  This article describes a design that allows
the registers to be periodically checked without adding a significant
amount of logic to the design.

      Figure 1 shows a typical data flow to control the configuration
registers for a storage and I/O control subsystem.  During the
initial configuration of the system the software will load these
registers across the Processor Bus.  In addition, if the software
needs to read the data back from one of these registers, a path is
provided where the data from all the registers is multiplexed
together and sent back across the same Processor Bus.  To parity
check these registers, a parity checker is added to each register.
Some additional logic is needed to 'OR' all the parity checker
outputs together and generate a parity error signal.

      The logic necessary to perform the parity checking, as shown in
Figure 1, will grow linearly with the number of registers in the
system.  With each register added, a parity...