Browse Prior Art Database

Finite State Machine That Allows a Soft (recoverable) Stop of a Processor System That Has a Memory Subsystem That Cannot Be Halted

IP.com Disclosure Number: IPCOM000101456D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 143K

Publishing Venue

IBM

Related People

Bakoglu, HB: AUTHOR [+3]

Abstract

Disclosed is a means for an external support processor to stop the main processor at any given instruction without causing a storage error due to partially completed DMA storage operations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 48% of the total text.

Finite State Machine That Allows a Soft (recoverable) Stop of a Processor System That Has a Memory Subsystem That Cannot Be Halted

       Disclosed is a means for an external support processor to
stop the main processor at any given instruction without causing a
storage error due to partially completed DMA storage operations.

      A processor chip set is used that includes built-in controls
that allow an external support processor access to all the internal
latches of the processor chip set.  This support processor gives the
hardware designers the ability to debug logic in the lab by stopping
the processor and observing the state of the internal logic.  This
ability is essential for debug of very dense chips.  Along with the
ability to inspect the internal state of the processor, it is also
necessary to be able to restart the processor and continue as if the
system had not been halted.  The logic chips that are not part of the
processor complex do not have the built-in logic that allows the
support processor to stop their execution.  These include the memory
card logic and the I/O chips.  If the processor is halted in the
middle of a memory operation or a DMA operation, the resulting data
in memory could not be guaranteed.  This article describes a design
that allows the external support processor to stop the system and
still be able to guarantee that any DMA transfer will complete
successfully.

      The processor system is shown in Figure 1.  The Instruction
Cache Unit (ICU), Floating-Point Unit (FPU) and Fixed-Point Unit
(FXU) receive data and instructions from the Data Cache Unit (DCU)
(instruc tions are not stored in the data cache, just passed through
the DCU to the ICU).  The FXU and ICU pass all requests for memory
transfers to the Storage Control Unit (SCU) through the Processor Bus
(PBUS), and all I/O memory requests are issued across the System I/O
bus (SIO bus).  Note that the ICU, FPU, FXU, DCU and SCU all have the
logic necessary for the support processor to stop execution.  The
memory, I/O bus Control Chip (IOCC) and devices on the F2 bus do not
allow execution to be halted.  To soft stop the processor at a
particular instruction, the address of the instruction is placed in a
control register of the ICU.  The ICU detects this address, and when
the instruction stream reaches this point, it will stop dispatching
instructions to the FXU and FPU.  Once it has received an indication
from the FPU and FXU that they have completed all instructions that
have been previously dispatched, including all memory transfers that
are associated with the instructions, it will issue a halt to all the
chips and turn over control to a support processor.  When the halt is
issued, there are no pending memory requests from the processor.
Since the I/O is not checked for an idle state, there may be I/O DMA
memory accesses still pending.  If the processor stops in the middle
of one of these memory operations, the resultin...