Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Field-Effect Transistor Shifted Logic

IP.com Disclosure Number: IPCOM000101457D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 103K

Publishing Venue

IBM

Related People

Moulic, J: AUTHOR

Abstract

Disclosed is a change to the structure of an Unbuffered-FET (Field-Effect Transistor) Logic gate which improves on its switching speed capabilities, while maintaining its high levels of integration. As such, the proposal of FSL (FET Shifted Logic) should have switching speeds comparable to LP-BFL (Low Powered - Buffered FET Logic), but with packing densities like that of SDFL (Schottky Diode FET Logic) and U-BFL (Unbuffered - FET Logic), and the lower power dissipation than with LP-BFL. The proposal made is thus: Replace the level shifting diode D1 in the U-BFL gate shown in Figure 1, with a JFET (Junction FET) connected as a load device, i.e., its gate and source tied together. This configuration is shown in Figure 2.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 61% of the total text.

Field-Effect Transistor Shifted Logic

       Disclosed is a change to the structure of an
Unbuffered-FET (Field-Effect Transistor) Logic gate which improves on
its switching speed capabilities, while maintaining its high levels
of integration.  As such, the proposal of FSL (FET Shifted Logic)
should have switching speeds comparable to LP-BFL (Low Powered -
Buffered FET Logic), but with packing densities like that of SDFL
(Schottky Diode FET Logic) and U-BFL (Unbuffered - FET Logic), and
the lower power dissipation than with LP-BFL. The proposal made is
thus: Replace the level shifting diode D1 in the U-BFL gate shown in
Figure 1, with a JFET (Junction FET) connected as a load device,
i.e., its gate and source tied together.  This configuration is shown
in Figure 2.  By properly selecting the pinch-off voltages, and the
IDSS values (drain-to-source saturation current) of the devices
comprising the gate, the circuit can be made input/output compatible,
and have a fast switching speed, by virtue of having significant
sink/source capability.  Simulation of a sample gate performed has
shown that switching speeds of 100 psec are possible with power
dissipation of 0.5 mW (Speed-Power Product of 50 fJoules).

      The combination of the transistors Q3 and Q4 (Figure 2)
provides a level shifting function, and can deliver a much larger
source/sink current than the U-BFL (Figure 1).  The reason for this
is simple:  To obtain a level shift of 0.5 to 1 V (necessary for a...