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Browse Prior Art Database

Multi-Bit Data Comparator Circuit

IP.com Disclosure Number: IPCOM000101461D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 58K

IBM

Related People

Nishihara, M: AUTHOR

Abstract

This article describes a new multi-bit data comparator circuit which is advantageous over conventional techniques in cirucit count and regularity. In this new circuit technique, a 4-bit magnitude comparator can be designed with less than 30 gates, and because of its regularity in physical layout, the circuit can be integrated with ease as a macro.

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Multi-Bit Data Comparator Circuit

circuit which is advantageous over conventional techniques in cirucit
count and regularity.  In this new circuit technique, a 4-bit
magnitude comparator can be designed with less than 30 gates, and
because of its regularity in physical layout, the circuit can be
integrated with ease as a macro.

Fig. 1 shows a circuit schematic according to the present
technique which compares two n-bit data.  Inputs INC 0-INC n and DEC
0-DEC n are signals from bit comparators which compare corresponding
bits of the n-bit data.  One of the bit comparators is shown in Fig.
2.  The bit comparator receives corresponding bits A(i) and B(i) of
n-bit data A and B and produces outputs INC(i) and DEC(i).  INC(i) is
low (L) and DEC(i) is high (H) when bit A(i)=1 and B(i)=0, and INC(i)
is high (H) and DEC(i) is low (L) when bit A(i)=0 and B(i)=1.  INC
and DEC are high (H) when A(i)=B(i).  These are shown in Table 1
which illustrates how 4-bit data A and B are compared.

The circuit of Fig. 1 is configured to start its operation from
the highest-order stage (bit n) down to the lowest-order stage (bit
0).  Each stage consists of two circuits 10 and 12 which generate
outputs IOUT and DOUT, respectively.  Assuming that a stage(i)
receives INC=L or DEC=L occurring first, then the stage produces
IOUT=L or DOUT=L to the next lower-order stage(i-1), which is in turn
propagated dow...