Browse Prior Art Database

Allocation of DMA Resources On Multiport Adapter

IP.com Disclosure Number: IPCOM000101472D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 113K

Publishing Venue

IBM

Related People

Adkins, JT: AUTHOR [+2]

Abstract

In order to best utilize intelligent adapter resources, a mechanism for suspending scheduling of ports awaiting DMA completion was developed. This was critical, as operating ports may require interrupt and offlevel processing services concurrently with data movement from the host computer system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Allocation of DMA Resources On Multiport Adapter

       In order to best utilize intelligent adapter resources, a
mechanism for suspending scheduling of ports awaiting DMA completion
was developed.  This was critical, as operating ports may require
interrupt and offlevel processing services concurrently with data
movement from the host computer system.

      In our application, a general-purpose base card with its own
processor, DMA controllers, timers and memory is used in conjunction
with a daughter card which contains hardware support defining the
electrical interfaces and number of ports supported.  The adapter
utilizes MICRO CHANNEL* Bus Master DMA, which is allowed to occur
simultaneously with other data movement chores on the adapter.
Streamlining the overlap of DMA data movement and CPU resources
ultimately determines the aggregate throughput of the adapter.

      In the communications environment provided by the Multiprotocol
Quad Port (MPQP) adapter, there are four communication ports
supporting several different types of electrical and data protocols.
They support data rates of 1200 to 64K bits/sec on each port
independently.  In order to transmit and receive data, data is
transferred across the MICRO CHANNEL.  All four ports must use a
single DMA channel to move data between the host and the adapter.
During Bus Master (first party) DMA, the adapter manages data
movement between the host and adapter. The data rate between the host
system to the adapter is much higher than the rate which the adapter
moves data on and off the line.

      Multiple "write" (outbound) data operations may be issued to a
port, regardless of the completion status of the preceding
operations.  By coupling the host and communications line this
loosely, the characteristics of each interface can be optimized.
Allowing the adapter to enqueue write data requests enables the host
to adapter DMA to occur concurrently with wire transmission of the
current write requests.  On termination of the current write request,
the next write can be started immediately, since the data has already
been moved onto the adapter. Corresponding performance benefits are
experienced on the receive (inbound) data paths.  Enabling multiple
ports to share a common resource for moving data between the host and
adapter requires a scheme for coordinating use of the DMA channel
with other system components.

      Allowing the two data movement mechanisms, with widely
disparate data rates, to occur simultaneously requires that a
mechanism exist to postpone actual transmission of the frame if the
host to adapter DMA has not completed yet. This is necessary because
the adapter, in using Bus Master DMA, controls the MICRO CHANNEL* to
bring the data to the adapter from the host.  This implies that, when
a transmit command is issued to the adapter, it cannot be sent off
the adapter to the network...