Browse Prior Art Database

Row And Column Address-Switchable Memory Addressing Circuit

IP.com Disclosure Number: IPCOM000101473D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Takahashi, Y: AUTHOR

Abstract

Disclosed is a memory addressing circuit which can switch row and column addresses to make good use of a segment- or page-organized memory which contains word or bit line failure.

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Row And Column Address-Switchable Memory Addressing Circuit

       Disclosed is a memory addressing circuit which can switch
row and column addresses to make good use of a segment- or
page-organized memory which contains word or bit line failure.

      Dynamic random-access memories are often divided into blocks
called segments or pages which extend in parallel along word or bit
lines.  With the segments extending along word lines, a failed bit
line will traverse all the segments, making all the segments
defective.  Conversely, with the segments extending along bit lines,
a failed word line will traverse all the segments, making all the
segments defective.  When such occurs, the defective memory must be
scrapped if word or bit redundancy is not provided.  The disclosed
technique allows such a defective memory to be used with only a
memory space loss of a single segment in the absence of word or bit
redundancy.

      In the figure which shows the present addressing circuit, row
and column addresses are multiplexed and applied to dynamic
random-access memory 10 through address multiplexing logic 22.  It is
assumed that in normal addressing, lower-order address bits A0-7 are
used for column addressing and higher-order address bits A8-15 are
used for row addressing.  It is also assumed that the memory 10 is
divided into segments 12-18 which extend along word lines to permit
page mode addressing.

      Now we assume that the memory 10 contains a failed...