Browse Prior Art Database

Test Mode for Dynamic Random-Access Memory Having On-Chip Error Correction Circuitry

IP.com Disclosure Number: IPCOM000101474D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Barth, JE: AUTHOR [+3]

Abstract

By outputting syndrome bits and data bits from a dynamic random-access memory (DRAM) to a static random-access memory (SRAM), outputs of the XOR logic of the error correction circuitry (ECC) become directly observable. Test time is reduced and a high degree of confidence in quality of DRAM memory chips having on-chip ECC is achieved.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Test Mode for Dynamic Random-Access Memory Having On-Chip Error Correction Circuitry

       By outputting syndrome bits and data bits from a dynamic
random-access memory (DRAM) to a static random-access memory (SRAM),
outputs of the XOR logic of the error correction circuitry (ECC)
become directly observable.  Test time is reduced and a high degree
of confidence in quality of DRAM memory chips having on-chip ECC is
achieved.

      Referring to Fig. 1B showing a write-back operation with ECC
on, data from the SRAM passes through XOR tree 10, generating check
bits to be stored in the DRAM.

      Referring to Fig. 1A showing a Fetch operation with ECC on,
data bits and check bits are read from the DRAM and pass through XOR
tree 10 generating syndrome bits which identify the location of a bad
bit.  Syndrome bits are put into the SRAM in place of the check bits.
The syndrome outputs are now directly available for an efficient
logic test.

      Referring to Figs. 2A and 2B, ECC OFF mode is used for DRAM
cell testing and a straight, uncorrected path is made between all
DRAM cells and SRAM cells in both fetch (Fig. 2A) and write-back
(Fig. 2B) operations.