Browse Prior Art Database

Hardware Design for a Programmable Interrupt Decoder

IP.com Disclosure Number: IPCOM000101475D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Dang, TH: AUTHOR

Abstract

Disclosed is a logic design for a programmable interrupt decoder hardware. Its function is selecting the winner of many requesting devices based upon their programmable priority values.

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Hardware Design for a Programmable Interrupt Decoder

       Disclosed is a logic design for a programmable interrupt
decoder hardware.  Its function is selecting the winner of many
requesting devices based upon their programmable priority values.

      Fig. 1 illustrates the overall picture of this hardware
decoder.  There are eight interrupt requesting devices which have
their request signals latched in an 8-bit register (R1 to R8).  The
priority of each requester (P1 to P8) is determined by a 3-bit value
in which 7 is the highest and 0 is the lowest priority value.  After
determining which one or no one will be the winner, this decoder will
send out eight 8-bit vectors (Va, Vb, Vc, Vd, Ve, Vf, Vg and Vh). The
winner of all interrupt requesting devices will have its 8-bit vector
value appear at V_OUT.

      Fig. 2 is the hardware design flow chart of the programmable
interrupt decoder.  Each interrupt device has its own defined
hardcode 8-bit vector (V1 to V7) or 0 if its request is not active
(0).  If one or more interrupt requests are active, then one of the
outputs, of Va to Vh will be a non-zero 8-bit value.  Otherwise, all
of them will have zero value.