Browse Prior Art Database

CMOS Double-Decked Inverter Latch Cell Layout for Low Area Occupancy And High Performance

IP.com Disclosure Number: IPCOM000101476D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Pham, DC: AUTHOR [+2]

Abstract

By laying out appropriate pairs of P transistors in adjacent rows and pairs of N transistors in an adjacent two rows, standard latch cell circuits are thereby comprised of "double-decked inverters" and can share some wiring. Substantial circuit layout area is saved and system performance is improved by this layout change in standard latch "books" within a design "library".

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

CMOS Double-Decked Inverter Latch Cell Layout for Low Area Occupancy And High Performance

       By laying out appropriate pairs of P transistors in
adjacent rows and pairs of N transistors in an adjacent two rows,
standard latch cell circuits are thereby comprised of "double-decked
inverters" and can share some wiring. Substantial circuit layout area
is saved and system performance is improved by this layout change in
standard latch "books" within a design "library".

      The figure is a standard complementary metal oxide
semiconductor (CMOS) latch circuit diagram having inverters A, B, C,
D, and E.  Each inverter is comprised of a P and an N transistor.
Inverter A is an input buffer, inverters B and C are a latch inverter
pair, and D and E are output buffers.  Scan clock input 2 gates scan
data input 4 through P-type pass gate transistor T1.  Functional
clock input 6 gates N-type pass gate transistor T2 to pass data clock
input at 8 after buffering by inverter A.  True and complement
outputs of the latch circuit are at T and C.

      The double-decked inverter layout is achieved by placing device
P2 of inverter C above transistor P1 of inverter B and device N2 of
inverter C below device N1 of inverter B in the physical layout.
Gate wiring connection 10 is shared between inverters C and E.  Gate
wiring 12 is shared between inverters B and D when these inverters
are similarly stacked. The diffusion area of P-type transistors in a
double- decked layout i...