Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Hardware Design for Bus Arbitration

IP.com Disclosure Number: IPCOM000101478D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 99K

Publishing Venue

IBM

Related People

Dang, TH: AUTHOR

Abstract

Disclosed is a logic circuit for bus arbitration hardware which will select the bus ownership for many requesting devices. It utilizes a rotational priority decoding scheme to determine their priorities. In this design, there are eight devices and each of them can have either a high priority request or a low priority request for bus access. In Fig. 1, Prio(0..7) represents eight-bit-latched priority value, and HiReq(0..7) and LoReq(0..7) represent eight latched high and low priority requests, respectively. Similarly, HiGrant(0..7) and LoGrant(0.. 7) represent eight latched grant signals for high and low priority requests, respectively. The highest priority requester is the one which has the associated priority bit set.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Hardware Design for Bus Arbitration

       Disclosed is a logic circuit for bus arbitration hardware
which will select the bus ownership for many requesting devices.  It
utilizes a rotational priority decoding scheme to determine their
priorities.  In this design, there are eight devices and each of them
can have either a high priority request or a low priority request for
bus access.  In Fig. 1, Prio(0..7) represents eight-bit-latched
priority value, and HiReq(0..7) and LoReq(0..7) represent eight
latched high and low priority requests, respectively. Similarly,
HiGrant(0..7) and  LoGrant(0.. 7) represent eight latched grant
signals for high and low priority requests, respectively.  The
highest priority requester is the one which has the associated
priority bit set.  The next highest priority requester has its
priority bit located to the immediate right of the set bit, the third
highest is the one to the right of that, and so on.  The priority of
eight requesting devices can be illustrated as:

                            (Image Omitted)

          Prio(0..7)                          Device number
         [[[[[[[[[[                           [[[[[[[[[[[[[
      bit0 --------> bit7         highest
    ------------------> lowest
 V             V           priority        priority
 a) 1 0 0 0 0 0 0 0  ==>  0 -> 1 -> 2
-> 3 -...