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Swap Circuit

IP.com Disclosure Number: IPCOM000101479D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Hornung, R: AUTHOR [+2]

Abstract

Fig. 1 shows the principle of the swap operation. When the swap control line (S0) is inactive (level "0"), outputs 10 and 20 are equal respectively to L0 and R0. When the swap control line (S0) becomes active, outputs 10 and 20 are respectively equal to R0 and L0.

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Swap Circuit

       Fig. 1 shows the principle of the swap operation. When
the swap control line (S0) is inactive (level "0"), outputs 10 and 20
are equal respectively to L0 and R0. When the swap control line (S0)
becomes active, outputs 10 and 20 are respectively equal to R0 and
L0.

      A novel implementation of the swap function is shown in Fig. 2
in CMOS technology. The proposed swap circuit is based on the use of
full transfer gates with inverters on both sides. These inverters
provide the required isolation of the transfer gates from the rest of
the logic.

      The disclosed swap gives a 18% gain in the number of
transistors (18 transistors (transistors of the input swap buffer not
included) compared to 22 transistors in standard circuits) and gives
a 50% gain in performance over present designs available in a
standard CMOS library.