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High Speed System I/O Bus Used to Connect a Processor to Multiple I/O Bus Controller Chips

IP.com Disclosure Number: IPCOM000101490D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 5 page(s) / 250K

Publishing Venue

IBM

Related People

Bailey, RN: AUTHOR [+3]

Abstract

In a high performance computer system there is a requirement to be able to attach multiple I/O buses to the main processor. These I/O buses may not be all the same type of bus. To allow this configuration, a high speed system I/O Bus (SIO Bus) was designed that would be internal to the processor complex and would allow multiple I/O Bus Controller chips (IOBCs) to be attached. Each of these controller chips would drive its own external I/O bus or buses. These external buses are where the I/O devices will be installed, and there is no restriction on the type of I/O bus design that is implemented. With this system I/O structure the processor complex is not restricted to one type of external I/O bus design.

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High Speed System I/O Bus Used to Connect a Processor to Multiple I/O Bus Controller Chips

       In a high performance computer system there is a
requirement to be able to attach multiple I/O buses to the main
processor.  These I/O buses may not be all the same type of bus.  To
allow this configuration, a high speed system I/O Bus (SIO Bus) was
designed that would be internal to the processor complex and would
allow multiple I/O Bus Controller chips (IOBCs) to be attached.  Each
of these controller chips would drive its own external I/O bus or
buses.  These external buses are where the I/O devices will be
installed, and there is no restriction on the type of I/O bus design
that is implemented.  With this system I/O structure the processor
complex is not restricted to one type of external I/O bus design.
Each machine built can have a different bus attached based on the
application that the system will perform and the performance of the
internal SIO Bus is not related directly to the performance of a
slower external bus and can support a wide range of bus speeds from
slow buses like the PC family 1 bus to a high speed optical bus.  The
internal system I/O bus described in this article will allow this
type of configuration.

      The SIO Bus is a dedicated internal bus used for communication
between the Processing Unit and the I/O BUS Controllers.  The bus
description contains a total of 96 signal I/Os, 86 of which are
bidirectional.  The bidirectional signals consist of a 72-bit
multiplexed address and data bus which includes 8 bits of parity, an
8-bit control bus with 1 parity bit and 5 control tags (address
valid, data valid, acknowledge, processor lock and checkstop).  The
other 10 unidirectional signals (4 bus request, 4 bus grant and 2
busy signals) are used for SIO Bus arbitration and by the I/O Control
Units to hold off I/O transfers.  See the figure for more detail.

      The SIO Bus supports the following transfers:  I/O loads and
stores, DMA block transfers and I/O interrupt requests to the
Processing Unit.  All DMA transfers or I/O store transfers are single
envelope.  In other words, the current transaction in progress must
be completed before a new request will be honored.  All I/O load
transfers have a disjoint reply packet.  The processor will issue the
I/O load request to one of the IOBCs and then release the SIO Bus
while it waits for the load data.  When the IOBC has the load data
ready, it will request the SIO Bus and transfer its data to the
processor.  Between the time the load instruction is issued and the
reply data is ready, the bus can be used for either DMA or interrupt
transfers.  This bus definition can only support one active I/O load
or store operation at a time.  Once a load request has been issued no
other load or store requests will be issued until the data for the
current load request is returned.

      The Processing Unit is the only SIO Bus master.  To get access
to t...