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Random-Access Memory Output Latch

IP.com Disclosure Number: IPCOM000101493D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Wissel, L: AUTHOR

Abstract

Access time of a random-access memory (RAM) array having a single- ended, non-differential, bit line is improved by using bit line pre- charge and capacitive charge sharing.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 57% of the total text.

Random-Access Memory Output Latch

       Access time of a random-access memory (RAM) array having
a single- ended, non-differential, bit line is improved by using bit
line pre- charge and capacitive charge sharing.

      Referring to the figure, clock F is high during an access and
low during restore.  Clock H is the complement of clock F.
Current-carrying capacity of array cell 10 bit line discharge device
(not shown) must be greater than that of transistor T4.  Also, bit
line capacitance C1 must be much greater than capacitance C4 on node
N4.

      During restore, clock H enables the inverter comprised of
P-type transistor T4 and N-type transistor T5.  Thus, transistors T4,
T5, T6, and T7 form a latch which retains data from the previous
array access.  Clock H also turns transistor T1 on, thereby
pre-charging bit line BL to high supply voltage VDD.

      If a previous latch state results in a 0 on node N4, clock H
opens transistor T3 when the new access begins. Thus, there is no
path to ground for the bit line charge when clock F causes transistor
T2 to conduct.  The bit line charge Q = VDD x C1 redistributes across
capacitance C1 and C4, leaving a final voltage of Vf = (VDD x C1)/(C1
C2) on bit line BL and on node N4.  Since capacitance C1 is much
greater than capacitance C4, Vf is near VDD causing transistor pair
T6 and T7 to switch node N6 low and turning on transistor T4 to
finish the voltage swing on node N4 to VDD and latch the value.

   ...