Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Reconfigurable Hardware for a Hardware Simulation Engine

IP.com Disclosure Number: IPCOM000101494D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Sweet, MD: AUTHOR

Abstract

Disclosed is a design for a hardware simulation engine. The hardware is designed so that it can support several different configurations. The engine contains three functional blocks (host interface, block description array (BDA) and current state array (CSA)) described below. The host interface consists of two first-in, first-out (FIFO) buffers to store packets of data between the simulation engine and the host. The BDA is a 512k x 100-bit array of dynamic RAM. This holds the model to be simulated. Each 100-bit word contains a gate definition or control instruction. The CSA consists of four 32k x 32-bit arrays of static RAM.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Reconfigurable Hardware for a Hardware Simulation Engine

       Disclosed is a design for a hardware simulation engine.
The hardware is designed so that it can support several different
configurations.  The engine contains three functional blocks (host
interface, block description array (BDA) and current state array
(CSA)) described below.  The host interface consists of two first-in,
first-out (FIFO) buffers to store packets of data between the
simulation engine and the host.  The BDA is a 512k x 100-bit array of
dynamic RAM.  This holds the model to be simulated.  Each 100-bit
word contains a gate definition or control instruction.  The CSA
consists of four 32k x 32-bit arrays of static RAM.  Three CSA
configurations are supported:  1) four 512k node arrays (one cycle
per gate evaluation); 2) two 1024k node arrays (two cycles per gate
evaluation); and 3) one 2048k node arrays (four cycles per gate
evaluation). In the first configuration, the address into each CSA
comes from one of the four-gate input operands in the BDA and each
array generates one operand per cycle.  In the second configuration,
two of the CSA arrays are stacked to become a single array.  Two of
the operands from the BDA are multiplexed onto the CSA addresses on
successive cycles to generate two operands.  The other pair of arrays
generates the other two operands in parallel.  In the third
configuration, all four arrays are stacked to generate a single
array.  The four operands from the BDA are multiplexed to each of the
arrays in turn to generate four outputs in four cycles.  To know
which four of the resulting sixteen operands to use, the control
logic uses the high-order bits from the BDA operands to determine
which are valid.  As an independent configuration option, the board
can be defined to be any one of the boards in a multi-board
configuration.  The board number is determined by a slot code on the
simulation bus; each board connected to the bus has a different code.

      During simulation, each of the boards must drive its node
results onto different lines of the simulation bus, and each board
updates its CSA with the new node data.  Thus, each board always has
a complete copy of...