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High Speed BICMOS Logic Circuits

IP.com Disclosure Number: IPCOM000101495D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Tomczak, JJ: AUTHOR

Abstract

By using a clocked logic concept, use of extra devices to control response of bipolar devices to ensure a rail-to-rail output swing is avoided. Thus, chip area is reduced and performance is improved for the bipolar complementary metal oxide silicon (BICMOS) family of logic circuits.

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High Speed BICMOS Logic Circuits

       By using a clocked logic concept, use of extra devices to
control response of bipolar devices to ensure a rail-to-rail output
swing is avoided.  Thus, chip area is reduced and performance is
improved for the bipolar complementary metal oxide silicon (BICMOS)
family of logic circuits.

      An example of implementation of the method is shown in the
figure, using a simple AND in the logic function region 2 of the
diagram.

      Precharge is achieved by P-type device T3, N-type device T4,
and P-type device T5.  As C1 goes high and C2 goes low, transistors
T4 and T5 turn on and T3 turns off.  Thus, NPN transistor T6 is
turned off and transistor T5 is turned on, causing output OUT to go
to VDD.  Since transistor T3 is turned off, all logic connected
between the drain of transistor T3 and the drain of T4 is disabled.

      Data is processed through the logic when C1 goes low and C2
goes high.  Assuming D0 to be low and D1 high, as C1 goes low and
C2 goes high, transistors T4 and T5 turn off and T3 and P-type
transistor T1 turn on causing base current to flow in transistor T6,
thus turning T6 on.  The output of transistor T6 then falls to
approximately ground potential. The circuit has a rail-to-rail output
when transistor T6 is allowed to go into saturation.  In most
applications, there is sufficient time during precharge for
transistor T6 to turn off.