Browse Prior Art Database

Precision Complementary Metal Oxide Silicon Interlock Circuit

IP.com Disclosure Number: IPCOM000101497D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Butler, E: AUTHOR [+2]

Abstract

This word line interlock circuit is turned on at array cell transfer device time by using an exact replica of the array cell tansfer device to detect transitions at the end of a reference word line. The precision achieved with this method results in a word line interlock circuit which tracks array cell sensitivity to variations in supply voltage (VDD), temperature, and process.

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Precision Complementary Metal Oxide Silicon Interlock Circuit

       This word line interlock circuit is turned on at array
cell transfer device time by using an exact replica of the array cell
tansfer device to detect transitions at the end of a reference word
line.   The precision achieved with this method results in a word
line interlock circuit which tracks array cell sensitivity to
variations in supply voltage (VDD), temperature, and process.

      Fig. 1 is a schematic of a P-channel array cell, wherein a
stored "1" level is defined as VDD and a stored "0"level is defined
as the threshold voltage (Vt) of transistor TA1.  Fig. 2 is a plot of
word line voltage vs. time, indicating turn-on characteristics of
device TA1 as a function of bias voltage.

      When the cell has a "1" stored, the top plate of capacitor C
becomes the source and TA1 turns on when VWL = VDD - Vt at time
T1. For a stored "0", TA1 turns on when VWL = Veq - Vt ,
where Veq is the bit line equalization potential or restore level
(near VDD/2), at time T0.  Veq becomes the source when Veq>Vt.

      Fig. 3 is a schematic of the precision word line interlock
circuit containing transistors TR1 (identical to array transistor
TA1) at the ends of references wordlines providing signals RWL0 and
RWLn.  Transistors TR1 are identical to array transistor TA1; i.e.,
they have the same layout, orientation, and are placed in the pumped
array N- well.  This circuit compares VWL to Veq via tra...