Browse Prior Art Database

Programmable Subcycle Timings

IP.com Disclosure Number: IPCOM000101500D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Smith, WJ: AUTHOR [+2]

Abstract

Dynamic random-access memory (DRAM) timing edges are triggered on subcycle boundaries by selecting events from a subcycle event network. Selection of event timings is programmable from a card interface, thereby allowing change of memory timings at card initialization time.

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This is the abbreviated version, containing approximately 100% of the total text.

Programmable Subcycle Timings

       Dynamic random-access memory (DRAM) timing edges are
triggered on subcycle boundaries by selecting events from a subcycle
event network.  Selection of event timings is programmable from a
card interface, thereby allowing change of memory timings at card
initialization time.

      Referring to the figure, a logic circuit (state machine) in
memory controller logic 10 determines when a particular memory signal
12 from latch 14 should change state.  The state machine selects a
programmable register 16 containing a coded amount of time to wait.
Content of register 16 is translated by selector circuits 18 and 20
into a timing pulse from subcycle event network 22.  A timing chart
of 8 pulses generated in network 22 within each cycle of a master
clock (granularity n = 8) is shown.  The event pulse generated by
selector circuit 20 turns latch 14 on or off.

      Although the edge event scheduling is fixed in the state
machine within controller logic 10, the time when the event occurs is
completely determined by the code in programmable timing register 16.
Default values are entered into register 16 at power-up time but the
values can be changed at any time.

      Granularity n of subcycle event network 22 is determined by
analysis of the basic system clock frequency, the technology of
implementation, and the DRAM requirements.