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Performance-Controlled CMOS Driver for Multi-Voltage Interfaces

IP.com Disclosure Number: IPCOM000101502D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Piro, RA: AUTHOR

Abstract

This performance controlled off-chip driver (OCD) allows interfacing to higher voltage networks. The design prevents current from flowing back into the driver's power supply and prevents snapback in output devices. The design maintains electric fields across gate insulation of output devices below damaging levels. Selectively turning on or off one or more control lines to parallel devices in the OCD's output provides a performance boost or reduction, as required.

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Performance-Controlled CMOS Driver for Multi-Voltage Interfaces

       This performance controlled off-chip driver (OCD) allows
interfacing to higher voltage networks.  The design prevents current
from flowing back into the driver's power supply and prevents
snapback in output devices.  The design maintains electric fields
across gate insulation of output devices below damaging levels.
Selectively turning on or off one or more control lines to parallel
devices in the OCD's output provides a performance boost or
reduction, as required.

      Referring to the figure, output devices, e.g., T1, T2, T3, T4,
T5, and T6 are split into series devices to reduce drain-to-source
voltage developed across an individual device when output pin voltage
at OUT exceeds supply voltage VDD.

      P-type output pull-up devices T1, T2, and T3 are in an N-well
biased, as indicated by arrow heads through P-type transistor T7 to
VDD.  The gate of bias device T7 is connected to the output pin of
the OCD.  When voltage on the output pin exceeds VDD of the driver,
device T7 turns off and the drain junction of pull-up device T3
forward biases. Thus, N-well voltage is pulled above VDD and latch-up
is prevented.

      Additional control circuitry is connected to the gates of
output P-type devices closest to VDD, e.g., T9, T12, and T13, to pull
these gates above VDD and thereby prevent current from flowing back
into the OCD power supply when the output pin rises above VDD.
P-type o...