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Pseudo-Random Pattern Self-Test of Arrays

IP.com Disclosure Number: IPCOM000101526D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Goodstal, GJ: AUTHOR

Abstract

This article describes the use and implementation of self-test using pseudo-random patterns to test imbedded arrays.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Pseudo-Random Pattern Self-Test of Arrays

       This article describes the use and implementation of
self-test using pseudo-random patterns to test imbedded arrays.

      High testability of imbedded arrays at the chip and/or board
level has always been a problem.  Often the design cannot afford to
allocate chip/card I/O to access the address register, data register
or read and write control which may be buried deeply in the chip
logic.  Array testing has become a large component of board test
costs, especially when deterministic testing using exhaustive test
schemes may take several minutes.  In addition, typical "stuck fault"
testing does not find AC faults.

      A random pattern generator, signature analyzer, and special
test control of the address register and read/write is built into the
chip.  Since these are built into the chip, there is no need to have
I/O allocated to access the data, address or read/write control
during test.  Also during test the address register is forced to
counter deterministically, hence eliminating a test variable.  Since
data and read/write are now the only variables, a reasonable length
random pattern test sequence can be applied exhaustively to the
array.  The exhaustive test sequence ensures that "disturb values"
will be applied to test for "near neighbor" sensitivity.  During this
testing, the address stepping and random pattern generation is
implemented so as to be driven by system clocks and at close to
system frequency thereby speeding testing and allowing AC fault
detection.

      Two test control modes are implemented (see the drawing):
1.   Array Scan Mode (ASM) is used during initialization to set a
"known value" into the array.  This allows the test to start with
predictable test data in the array. When in ASM mode, the address
re...