Browse Prior Art Database

Optical Clock Distribution for Computing Systems

IP.com Disclosure Number: IPCOM000101530D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 144K

Publishing Venue

IBM

Related People

Donner, EO: AUTHOR [+3]

Abstract

Clock skew plays a major factor for computer cycle time. Through this invention, we can significantly reduce the clock skew more than one third than the electric clock.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Optical Clock Distribution for Computing Systems

       Clock skew plays a major factor for computer cycle time.
Through this invention, we can significantly reduce the clock skew
more than one third than the electric clock.

      An example of current electrical clock block diagram is shown
in Fig. 1.  A master oscillator on the oscillator card A generates
pulses which are sent to OSC control chip B. The signals are then
distributed to clock control chip C on various boards.
Synchronizations and maintenance are performed on clock control chip
C.  Types of clock signals which are generated through trailing edges
and leading edges of the master clock are sent to the TCM modules.
The clock power chip D, which is inside the TCM, receives the signals
and distributes them to all the logic chips G and array chips H
within the TCM.

      An example of proposed optical clock block diagram is shown in
Fig. 2.  Light source A can be a solid-state laser, gas laser, or
semiconductor laser, mode locked which emit optical pulses with
desirable frequencies.  The semiconductor lasers and solid-state
lasers are preferred due to the compact sizes and ease of
maintenance.  These optical pulses are sent to fibers through
coupling elements. These coupling elements may be lenses or beam
splitters to ensure uniform distribution of light pulses into the
fiber bundles.  The fibers should be cut to the same length.  A 1 mm
length difference will result in 5 ps delay difference.  The optical
clock signals are then transmitted to all the modules F containing
chips.  Each module contains several waveguides C, optical detectors
D and clock chips E.  The fibers are coupled through waveguides into
the TCM.  The accurate delay control can be further adjusted by
waveguide C in front of the detector D.  A passive control can be
achieved by laser trimming of the waveguides for um accuracy.  The
active control can be achieved by electrical or magnetic signals to
adjust the optical pulse delay.  The optical detectors D can be any
solid-state device (such as Si, Ge, GaAs, GaInAsP, etc.) which can be
integrated onto Chip D or separated from Chip E and connected through
electrical wiring.  The chips D, E:
 1.  translate optical signals into electrical signals plus
amplification,
      2.  provide types of clocks at desired frequences and phases,
and
      3.  perform maintenance functions and synchronization.

      The new clock trains are then sent to logic chips and array
chips electrically through module wiring.

      A large clock skew reduction can be achieved; the largest
saving in the skew is due to Chip C-Board-TCM-Chip D connections.  A
skew budget is added to chip E due to the maintenance and synchronize
functions which was performed in the board level as in the sample
electronics case.  An optimistic case depending on the current
state-of-art projection could reduce the skew by up to 80% of the
electronic distributi...