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I/O Bus Design That Improves Processor Performance by Allowing Early Address Validation During an I/O Store Operation

IP.com Disclosure Number: IPCOM000101533D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Bailey, RN: AUTHOR [+3]

Abstract

This article describes a system I/O bus design that allows the processor to run I/O load and store operations with precise interrupts without causing excessive delays in execution stream of the processor. To achieve the goal of precise interrupts, when an I/O store operation is issued the processor must stop execution of instructions until the I/O controller has checked the address of the store to verify that it is correct. With a typical I/O bus the processor would have to wait until all the data has been transferred before the I/O controller will have access to the I/O bus to transfer the error condition back. In a processor running at a high system clock rate (25 Mhz and above), this transfer could take many system cycles. Fig.

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I/O Bus Design That Improves Processor Performance by Allowing Early Address Validation During an I/O Store Operation

       This article describes a system I/O bus design that
allows the processor to run I/O load and store operations with
precise interrupts without causing excessive delays in execution
stream of the processor.  To achieve the goal of precise interrupts,
when an I/O store operation is issued the processor must stop
execution of instructions until the I/O controller has checked the
address of the store to verify that it is correct.  With a typical
I/O bus the processor would have to wait until all the data has been
transferred before the I/O controller will have access to the I/O bus
to transfer the error condition back.  In a processor running at a
high system clock rate (25 Mhz and above), this transfer could take
many system cycles.  Fig. 1 shows how this transfer would take place
in a system where the processor allowed I/O store operations up to
128 bytes in length and the system I/O bus is 8 bytes wide.

      In this implementation, an additional signal was added to the
system I/O Bus to allow the I/O controller to signal the processor
when it had completed the address verification.  This signal, the
processor lock in Fig. 2, is activated when the I/O controller
received the I/O store operation, and as long as it is active, the
processor would remain locked (execution of instructions is halted).
When the I/O controller completed the addre...