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Browse Prior Art Database

Fetch Decisions With Invalid Cache Entries

IP.com Disclosure Number: IPCOM000101539D
Original Publication Date: 1990-Aug-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

This article describes a method for making fetch decisions based on information recorded at invalidated cache entries in a multiprocessor environment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Fetch Decisions With Invalid Cache Entries

       This article describes a method for making fetch
decisions based on information recorded at invalidated cache entries
in a multiprocessor environment.

      In future processors caches will become larger and there will
be more central processors (CPs) in a multiprocessor (MP) system.  As
a result there will be more invalid entries in each CP cache due to
cross-invalidates (XI-invalidates).  From experiments we observe
that, in a typical commercial application, many of such
XI-invalidated data lines are relatively frequently accessed in the
system. As a result, in future environment, it is more likely that an
XI-invalidated line at a processor cache will get accessed again by
the CP before such an invalidated entry gets replaced from its
directory. .sp

      Based on the above observations, better cache access decisions
may be devised with information recorded in those XI-invalidated line
entries.  In conventional designs, an invalidated cache directory
entry will be regarded as obsolete completely.  In this invention
information recorded in such entries will be used to assist fetch
miss decisions. In the following we will illustrate the concept with
an example MP cache design.

      Consider a design in which exclusive (EX) state is used to
manage MP cache coherence.  Each line entry in a cache directory has
(at least) a validity bit (V-bit) and an exclusivity bit (EX-bit).  A
line can be stored into by the CP only when its EX-bit is on in
the directory.  When a processor cache first acquires EX state on a
line, all remote copies of the line should be properly invalidated. A
cache line is invalid...